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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 135 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile program and data memories ? 64/128k bytes of in-system self-programmable flash ? endurance: 100,000 write/erase cycles ? optional boot code section with independent lock bits ? in-system programming by on-chip bo ot program hardware activated after reset ? true read-while-write operation ? 2k/4k (64k/128k flash version) bytes eeprom ? endurance: 100,000 write/erase cycles ? 4k/8k (64k/128k flash ver sion) bytes internal sram ? up to 64k bytes optional external memory space ? programming lock fo r software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits through the jtag interface ? usb 2.0 full-speed/low-speed device and on-the-go module ? complies fully with: ? universal serial bus specification rev 2.0 ? on-the-go supplement to the usb 2.0 specification rev 1.0 ? supports data transfer rates up to 12 mbit/s and 1.5 mbit/s ? usb full-speed/low speed device module with interrupt on transfer completion ? endpoint 0 for control transfers : up to 64-bytes ? 6 programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers ? configurable endpoints size up to 256 bytes in double bank mode ? fully independant 832 bytes usb dpram for endpoint memory allocation ? suspend/resume interrupts ? power-on reset and usb bus reset ? 48 mhz pll for full-speed bus operation ? usb bus disconnection on microcontroller request ? usb otg: ? supports host negotiation protocol (hnp) and session request protocol (srp) for otg dual-role devices ? provide status and control signals for software implementation of hnp and srp ? provides programmable times required for hnp and srp ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? two16-bit timer/counter with separate prescaler, compare- and capture mode ? real time counter with separate oscillator ? two 8-bit pwm channels 8-bit microcontroller with 64/128k bytes of isp flash and usb controller at90usb646 at90usb647 at90usb1286 at90usb1287 preliminary
2 7593a?avr?02/06 at90usb64/128 ? six pwm channels with programma ble resolution from 2 to 16 bits ? output compare modulator ? 8-channels, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? byte oriented 2-wire serial interface ? programmable watchdog timer wit h separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power- save, power-down, standby, and extended standby ? i/o and packages ? 48 programmable i/o lines ? 64-lead tqfp and 64-lead qfn ? operating voltages ? 2.7 - 5.5v ? 2.2 - 5.5v (check availabilty) ? operating temperature ? industrial (- 40c to +85c) ? maximum frequency ? 8 mhz at 2.7v - industrial range ? 16 mhz at 4.5v - industrial range 3 7593a?avr?02/06 at90usb64/128 1. pin configurations figure 1-1. pinout at90usb64/128-tqfp 4 7593a?avr?02/06 at90usb64/128 figure 1-2. pinout at90usb64/128-qfn note: the large center pad underneath the mlf package s is made of metal and internally connected to gnd. it should be soldered or glued to the boar d to ensure good mechanical stability. if the center pad is left unconnected, the package might loosen from the board. 1.1 disclaimer typical values contained in th is datasheet are based on simulati ons and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized. 2. overview the at90usb64/128 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful in structions in a single clock cycle, the 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 33 15 47 46 48 45 44 43 42 41 40 39 38 37 36 35 34 17 18 20 19 21 22 23 24 25 26 27 29 28 32 31 30 52 51 50 49 64 63 62 53 61 60 59 58 57 56 55 54 at90usb128 (64-lead qfn top view) index corner avcc gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck ) pf5 (adc5/tms ) pf6 (adc6/tdo ) pf7 (adc7/tdi) gnd vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) (int.7/ain.1/uvcon) pe7 uvcc d- d+ ugnd ucap vbus (iuid) pe3 (ss/pcint0) pb0 (int.6/ain.0) pe6 (pcint1/sclk) pb1 (pdi/pcint2/mosi) pb2 ( pdo/pcint3/miso) pb3 (pcint4/oc.2a) pb4 (pcint5/oc.1a) pb5 (pcint6/oc.1b) pb6 ( pcint7/oc.0a/oc.1c) pb7 (int4/tosc1) pe4 (int.5/tosc2) pe5 vcc gnd xtal2 xtal1 (oc0b/scl/int0) pd0 (oc2b/sda/int1) pd1 (rxd1/int2) pd2 (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 (t1) pd6 (t0) pd7 reset pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe2 (ale/hwb) pc7 (a15/ic.3/clk0 ) pc6 (a14/oc.3a) pc5 (a13/oc.3b) pc4 (a12/oc.3c) pc3 (a11/t.3) pc2 (a10) pc1 (a9) pc0 (a8) pe1 (rd) pe0 (wr) 5 7593a?avr?02/06 at90usb64/128 at90usb64/128 achieves thro ughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set wit h 32 general purpose working registers. all the 32 registers are directly connected to the arithm etic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. program counter stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. port b data dir. reg. port e data dir. reg. port a data dir. reg. port d data register port b data register port e data register port a data register port d interrupt unit eeprom spi usart0 status register z y x alu port b drivers port e drivers port a drivers port f drivers port d drivers port c drivers pb7 - pb0 pe7 - pe0 pa7 - pa0 pf7 - pf0 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comparator pc7 - pc0 internal oscillator watchdog timer 8-bit data bus avcc usb timing and control oscillator oscillator calib. osc data dir. reg. port c data register port c on-chip debug jtag tap programming logic boundary- scan data dir. reg. port f data register port f adc por - bod reset pd7 - pd0 data dir. reg. port g data reg. port g port g drivers pg4 - pg0 two-wire serial interface pll 6 7593a?avr?02/06 at90usb64/128 the at90usb64/128 provides the following featur es: 64/128k bytes of in-system programma- ble flash with read-while-wri te capabilities, 2k/4k bytes eeprom, 4k/8k bytes sram, 48 general purpose i/o lines, 32 general purpose work ing registers, real time counter (rtc), four flexible timer/counters with compare modes and pwm, one usart, a byte oriented 2-wire serial interface, a 8-channels, 10-bit adc with optional differential input stage with programma- ble gain, programmable watchdog timer with inter nal oscillator, an spi se rial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming and six software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi por t, and interrupt system to continue function- ing. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asyn- chronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mo de stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switch ing noise during adc co nversions. in standby mode, the crystal/resonator oscillator is runn ing while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillato r and the asynch ronous timer continue to run. the device is manufactured using atmel?s high- density nonvolatile memo ry technology. the on- chip isp flash allows the prog ram memory to be reprogrammed in -system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applicatio n flash memory. software in the boot flash section will continue to run while the application flash section is updated, pr oviding true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel at90usb64/128 is a powerf ul microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the at90usb64/128 avr is supported with a fu ll suite of program and system development tools including: c compilers, ma cro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. 2.2 pin descriptions 2.2.1 vcc digital supply voltage. 2.2.2 gnd ground. 2.2.3 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive ch aracteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the function s of various special features of the at90usb64/128 as listed on page 80 . 7 7593a?avr?02/06 at90usb64/128 2.2.4 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive ch aracteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving capabilities than the other ports. port b also serves the function s of various special features of the at90usb64/128 as listed on page 81 . 2.2.5 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the at90usb64/128 as listed on page 84 . 2.2.6 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various s pecial features of the at 90usb64/128 as listed on page 85 . 2.2.7 port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive ch aracteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the function s of various special features of the at90usb64/128 as listed on page 88 . 2.2.8 port f (pf7..pf0) port f serves as analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o po rt, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7( tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. 8 7593a?avr?02/06 at90usb64/128 2.2.9 d- usb full speed / low speed nega tive data upstream port. 2.2.10 d+ usb full speed / low speed positive data upstream port. 2.2.11 ugnd usb ground. 2.2.12 uvcc usb pads internal regulator input supply voltage. 2.2.13 ucap usb pads internal regulator outp ut supply voltage. should be connected to an external capac- itor (1f). 2.2.14 vbus usb vbus monitor and otg negociations. 2.2.15 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 8-1 on page 59 . shorter pulses are not guaranteed to generate a reset. 2.2.16 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.2.17 xtal2 output from the invert ing oscillator amplifier. 2.2.18 avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally con- nected to v cc , even if the adc is not used. if the ad c is used, it should be connected to v cc through a low-pass filter. 2.2.19 aref this is the analog reference pin for the a/d converter. 3. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. these code examples assume that the part specif ic header file is included before compilation. for i/o registers located in extended i/o map, "i n", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbrc", "sbr", and "cbr". 9 7593a?avr?02/06 at90usb64/128 4. avr cpu core 4.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peri pherals, and handle interrupts. 4.2 architectural overview figure 4-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipe lining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 10 7593a?avr?02/06 at90usb64/128 the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be us ed as three 16-bit indirect add ress register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is up dated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole addres s space. most avr instructions have a single 16-bit word for- mat. every program memory address co ntains a 16- or 32-bit instruction. program flash memory space is divided in tw o sections, the boot program section and the application program section. both sections have dedicated loc k bits for write and read/write protection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in th e general data sram, and consequently the stack size is only limited by the total sram size an d the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing mo des supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control regi sters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a s eparate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interr upt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the at90usb64/128 has extended i/o space from 0x60 - 0x0ff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 4.3 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immedi ate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multip lier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 11 7593a?avr?02/06 at90usb64/128 4.4 status register the status register contains information about the result of the most recently executed arith- metic instruction. this information can be used fo r altering program flow in order to perform conditional operations. note that the status re gister is updated after all alu operations, as specified in the instructio n set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically st ored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of t he interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interr upts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instructio n set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bi t as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 i thsvnzcsreg read/write r/w r/w r/ wr/wr/wr/wr/wr/w initial value00000000 12 7593a?avr?02/06 at90usb64/128 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. 4.5 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 4-2 shows the structure of the 32 genera l purpose working registers in the cpu. figure 4-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 4-2 , each register is also assigned a data memory address, mapping them directly into the first 32 loca tions of the user data space. although not being physically imple- mented as sram locations, this memory organizati on provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 4.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functi ons to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-3 . 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 13 7593a?avr?02/06 at90usb64/128 figure 4-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (s ee the instruction set reference for details). 4.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer r egister always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory location s. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the da ta sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x0100. the initial value of the sta ck pointer is the last address of the internal sram. the stack pointer is decremented by o ne when data is pushed onto the stack with the push instruction, and it is decremented by three when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by three when data is popped from the stack with return from subr outine ret or return from interrupt reti. the avr stack pointer is implemented as two 8-bi t registers in the i/o space. the number of bits actually used is implementation dependent. no te that the data space in some implementa- tions of the avr architecture is so small that onl y spl is needed. in this case, the sph register will not be present. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 1514131211109 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 1 0 0 0 0 0 11111111 14 7593a?avr?02/06 at90usb64/128 4.6.1 extended z-pointer register for elpm/spm - rampz for elpm/spm instructions, the z-pointer is a concatenation of rampz, zh, and zl, as shown in figure 4-4. note that lpm is not affected by the rampz setting. figure 4-4. the z-pointer used by elpm and spm the actual number of bits is implementation dependent. unused bits in an implementation will always read as zero. for compatibility with future devices, be su re to write these bits to zero. 4.7 instruction execution timing this section describes the general access timi ng concepts for instructi on execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-acc ess register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-5. the parallel instruction fetche s and instruction executions figure 4-6 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. bit 7654321 0 rampz 7 rampz 6 rampz 5 rampz 4 rampz 3 rampz 2 rampz1 rampz0 rampz read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit ( individually) 707070 rampz zh zl bit (z-pointer) 23 16 15 8 7 0 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2 nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu 15 7593a?avr?02/06 at90usb64/128 figure 4-6. single cycle alu operation 4.8 reset and in terrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be writ ten logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security . see the section ?memory program- ming? on page 368 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 69 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control r egister (mcucr). refer to ?interrupts? on page 69 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?memory programming? on page 368 . when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instru ction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program co unter is vectored to th e actual interrupt vec- tor in order to execute the interrupt handli ng routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the in terrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corr esponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main prog ram and execute one more instruction before any pending interrupt is served. total execution time r egister operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 16 7593a?avr?02/06 at90usb64/128 note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be ex ecuted after the cli instru ction, even if it occurs simultaneously with the cli instruction. the following example shows how th is can be used to avoid interrupts during the timed eeprom write sequence.. when using the sei instruction to enable interr upts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 18 7593a?avr?02/06 at90usb64/128 5. avr at90usb64/128 memories this section describes the different memories in the at90usb64/128. the avr architecture has two main memory spaces, the data memory and the program memory space. in addition, the at90usb64/128 features an eeprom memory for data storage. all three memory spaces are linear and regular. notes: 1. byte address. 2. word (16-bit) address. 5.1 in-system reprogrammabl e flash program memory the at90usb64/128 contains 128k bytes on-chip in-system reprogrammable flash memory for program storage. since all avr instructions are 16 or 32 bits wide, the flash is organized as 64k x 16. for software security, the flash progr am memory space is divided into two sections, boot program section and application program section. the flash memory has an en durance of at le ast 100,000 write/erase cycles. the at90usb64/128 program counter (pc) is 16 bi ts wide, thus addressing the 128k program table 5-1. memory mapping. memory mnemonic at90usb64 at90usb128 flash size flash size 64 k bytes 128k bytes start address - 0x00000 end address flash end 0x0ffff (1) 0x7fff (2) 0x1ffff (1) 0xffff (2) 32 registers size - 32 bytes start address - 0x0000 end address - 0x001f i/o registers size - 64 bytes start address - 0x0020 end address - 0x005f ext i/o registers size - 160 bytes start address - 0x0060 end address - 0x00ff internal sram size isram size 4 k bytes 8 k bytes start address isram start 0x0100 end address isram end 0x10ff 0x20ff external memory size xmem size 0-64 k bytes start address xmem start 0x1100 0x2100 end address xmem end 0xffff eeprom size e2 size 2 k bytes 4k bytes start address - 0x0000 end address e2 end 0x07ff 0x0fff 19 7593a?avr?02/06 at90usb64/128 memory locations. the operation of boot program section and associated boot lock bits for software protection are described in detail in ?memory programming? on page 368 . ?memory programming? on page 368 contains a detailed description on flash data serial downloading using the spi pins or the jtag interface. constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory instruction description and elpm - extended load program memory instruction description). timing diagrams for instruction fetc h and execution are presented in ?instruction execution tim- ing? on page 14 . figure 5-1. program memory map 5.2 sram data memory figure 5-2 shows how the at90usb64/128 sram memory is organized. the at90usb64/128 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in the opcode for the in and out instructions. for the extended i/o space from $060 - $1ff in sram, only the st/sts/std and ld/lds/ldd instruc- tions can be used. the first 4,608/8,704 data memo ry locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram . the first 32 locations address the register file, the next 64 location the standard i/o memory, then 416 locations of extended i/o memory and the next 8,192 locations address the internal data sram. 0x00000 program memory application flash section boot flash section flash end 20 7593a?avr?02/06 at90usb64/128 an optional external data sr am can be used with the at90usb6 4/128. this sram will occupy an area in the remaining address locations in the 64k address space. th is area starts at the address following the internal sram. the regist er file, i/o, extended i/o and internal sram occupies the lowest 4,608/8,704 bytes, so when using 64kb (65,536 bytes) of external memory, 60,478/56,832 bytes of external memory are available. see ?external memory interface? on page 29 for details on how to take advantage of the external memory map. when the addresses accessing the sram memory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. when the internal data memories are accessed, the read and write strobe pins (pe0 and pe1 ) are inactive during the whole access cycle. external sram operation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycle. if the stack is placed in external sram, interrupts, subroutine calls and returns take three clock cycles extra because the three-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe- line memory access. when external sram interfac e is used with wait-state, one-byte external access takes two, three, or four additional cl ock cycles for one, two, and three wait-states respectively. interrupt s, subroutine calls and returns will n eed five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states. the five different addressing modes for the data me mory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and in direct with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, and the 8,192 bytes of internal data sram in the at90usb64/128 are all accessible through all these addressing modes. the reg- ister file is described in ?general purpose register file? on page 12 . 21 7593a?avr?02/06 at90usb64/128 figure 5-2. data memory map 5.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 5-3 . 32 r eg i st e r s 64 i/o r eg i st e r s i n t e r na l s r a m ( 8192 x 8 ) $0000 - $001 f $0020 - $005 f $ ffff $0060 - $00 ff d a t a m e m o r y e xt e r na l s r a m ( 0 - 64 k x 8 ) 160 e xt i/o r eg . xmem start isram end isram start 22 7593a?avr?02/06 at90usb64/128 figure 5-3. on-chip data sram access cycles 5.3 eeprom data memory the at90usb64/128 contains 2k/4k bytes of da ta eeprom memory. it is organized as a sep- arate data space, in which single bytes ca n be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specifyi ng the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see page 382 , page 387 , and page 371 respectively. 5.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 5-3 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instruc- tions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on po wer-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom co rruption? on page 27. for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for four clock cycles before th e next instruction is executed. when the eeprom is written, the cpu is halte d for two clock cycles before the next instruction is executed. 5.3.2 the eeprom address register ? eearh and eearl clk wr rd data data a ddress address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction bit 1514131211 10 9 8 ????eear11eear10eear9eear8eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 23 7593a?avr?02/06 at90usb64/128 ? bits 15..12 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bits 11..0 ? eear8..0: eeprom address the eeprom address r egisters ? eearh and eearl specify the eeprom address in the 4k bytes eeprom space. the eeprom data bytes are addressed lin early between 0 and 4096. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 5.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 5.3.4 the eeprom control register ? eecr ? bits 7..6 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines which prog ramming action th at will be trig- gered when writing eepe. it is pos sible to program data in one at omic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 5-2 . while eepe is set, any write to eepmn will be ignored. du ring reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. 76543 2 10 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value0000x x xx xxxxx x xx bit 76543210 msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 765432 10 ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 24 7593a?avr?02/06 at90usb64/128 ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eepro m ready interrupt generates a constant inter- rupt when eepe is cleared. ? bit 2 ? eempe: eeprom master programming enable the eempe bit determines whether setting eepe to one causes the eeprom to be written. when eempe is set, setting eepe within four cloc k cycles will write data to the eeprom at the selected address if eempe is zero, setting eepe will have no effect. when eempe has been written to one by software, ha rdware clears the bit to zero after four clock cycles. see the description of the eepe bit fo r an eeprom write procedure. ? bit 1 ? eepe: eeprom programming enable the eeprom write enable signal eepe is the wr ite strobe to the eeprom. when address and data are correctly set up, the eepe bit must be written to one to write the value into the eeprom. the eempe bit must be wr itten to one be fore a logical one is written to eepe, other- wise no eeprom write takes pl ace. the following pr ocedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until selfprgen in spmcsr becomes zero. 3. write new eeprom addres s to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writing a zero to eepe in eecr. 6. within four clock cycles after sett ing eempe, write a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is comp leted before initiating a new eeprom write. step 2 is only relevant if the software contai ns a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?memory pro- gramming? on page 368 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine ac cessing the eeprom is interrupting another eeprom acce ss, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global in terrupt flag cleared during all the steps to avoid these problems. table 5-2. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 25 7593a?avr?02/06 at90usb64/128 when the write access time has elapsed, the eepe bit is cleared by hardware. the user soft- ware can poll this bit and wait for a zero befo re writing the next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the re ad strobe to the eeprom . when the correct address is set up in the eear regi ster, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read ac cess takes one instruction, and the reques ted data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a write operation is in progress, it is neither possi ble to read the e eprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 5-3 lists the typical pro- gramming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts ar e controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during ex ecution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any on going spm command to finish. table 5-3. eeprom programming time symbol number of calibrated rc o scillator cycles typ programming time eeprom write (from cpu) 26,368 3.3 ms 26 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. assembly code example (1) eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example (1) void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 29 7593a?avr?02/06 at90usb64/128 5.5 external memory interface with all the features the external memory interf ace provides, it is well suited to operate as an interface to memory devices such as external sram and flash, and peripherals such as lcd- display, a/d, and d/a. the main features are: ? four different wait-state setti ngs (including no wait-state). ? independent wait-state setting for different external memory sect ors (configurable sector size). ? the number of bits dedicated to address high byte is selectable. ? bus keepers on data lines to minimize current consumption (optional). 5.5.1 overview when the external memory (xmem) is enabled , address space outside the internal sram becomes available using the dedicated external memory pins (see figure 2-1 on page 5 , table 10-3 on page 80 , and table 10-9 on page 84 ). the memory configuration is shown in figure 5-4 . figure 5-4. external memory with sector select 5.5.2 using the external memory interface the interface consists of: ? ad7:0: multiplexed low-order address bus and data bus. ? a15:8: high-order address bus (configurable number of bits). ? ale: address latch enable. ?rd : read strobe. ?wr : write strobe. the control bits for the external memory interf ace are located in two registers, the external memory control register a ? xmcra, and the ex ternal memory control register b ? xmcrb. m e m o r y c on f igu r a t ion a 0 x 0000 e xt e r na l m e m o r y ( 0 - 60 k x 8 ) 0 x ffff i n t e r na l m e m o r y s r l [ 2 .. 0 ] s r w 11 s r w 10 s r w 01 s r w 00 l o w e r s e ct o r u ppe r s e ct o r isram end xmem start 30 7593a?avr?02/06 at90usb64/128 when the xmem interface is enabled, the xmem interface will override th e setting in the data direction registers that corresponds to the ports dedicated to the xmem interface. for details about the port override, see the alternate functions in section ?i/o-ports? on page 73 . the xmem interface will auto-detect whether an access is internal or external. if the access is external, the xmem interface will output address, data, and the control si gnals on the ports according to fig- ure 5-6 (this figure shows the wave forms without wait -states). when ale goes from high-to-low, there is a valid address on ad7:0. ale is low during a data transfer. when the xmem interface is enabled, also an internal access will caus e activity on address, data and ale ports, but the rd and wr strobes will not toggle duri ng internal access . when the external memory interface is disabled, the normal pin and data direction se ttings are used. note that when the xmem inter- face is disabled, the address space above the internal sram boundary is not mapped into the internal sram. figure 5-5 illustrates how to connect an exte rnal sram to the avr using an octal latch (typically ?74 x 573? or equiva lent) which is transpar ent when g is high. 5.5.3 address latch requirements due to the high-speed operation of the xram in terface, the address latch must be selected with care for system frequencies above 8 mhz @ 4v and 4 mhz @ 2.7v. when operating at condi- tions above these frequencies, the typical old style 74hc series latch becomes inadequate. the external memory interface is designed in complia nce to the 74ahc series latch. however, most latches can be used as long they comply with the main timing parameters. the main parameters for the address latch are: ? d to q propagation delay (t pd ). ? data setup time before g low (t su ). ? data (address) hold time after g low ( th ). the external memory interface is designed to guaranty minimum address hold time after g is asserted low of t h = 5 ns. refer to t laxx_ld /t llaxx_st in ?external data memory timing? tables 30- 7 through tables 30-13 on pages 408 - 411. the d-to-q propagation delay (t pd ) must be taken into consideration when calculating the access time requirement of the external component. the data setup time before g low (t su ) must not exceed address valid to ale low (t avllc ) minus pcb wiring delay (dependent on the capacitive load). figure 5-5. external sram connected to the avr d[7:0] a[7:0] a[15:8] rd wr sram dq g ad7:0 ale a15:8 rd wr avr 31 7593a?avr?02/06 at90usb64/128 5.5.4 pull-up and bus-keeper the pull-ups on the ad7:0 ports may be activated if the corresponding port register is written to one. to reduce power consumpti on in sleep mode, it is recomme nded to disable the pull-ups by writing the port register to zero before entering sleep. the xmem interface also provides a bus-keeper on the ad7:0 lines. the bus-keeper can be dis- abled and enabled in software as described in ?external memory control register b ? xmcrb? on page 34 . when enabled, the bus-ke eper will keep the previous value on the ad7:0 bus while these lines are tri-stated by the xmem interface. 5.5.5 timing external memory devices have different timing requirements. to meet these requirements, the xmem interface provides four different wait-states as shown in table 5-5 . it is important to con- sider the timing specific ation of the external memory device before selecting th e wait-state. the most important parameters are the access time fo r the external memory compared to the set-up requirement. the access time for th e external memory is defined to be the time from receiving the chip select/address until the data of this addr ess actually is driven on the bus. the access time cannot exceed the time from the ale pulse must be asserted low until data is stable during a read sequence (see t llrl + t rlrh - t dvrh in tables 30-6 through tables 30-13 on pages 408 - 411). the different wait-states are set up in software. as an additional feature, it is possible to divide the external memory space in two sectors wit h individual wait-state settings. this makes it possible to connect two differen t memory devices with different timing requirements to the same xmem interface. fo r xmem interface timing details, please refer to tables 30-6 through tables 30-13 and figure 30-7 to figure 30-10 in the ?external data memory timing? on page 408 . note that the xmem interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. t he skew between the internal and external clock (xtal1) is not guarantied (varies between devices temperature, and supply voltage). conse- quently, the xmem interface is not suited for synchronous operation. figure 5-6. external data memory cycles without wait-state (srwn1=0 and srwn0=0) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in perio d t4 is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) 32 7593a?avr?02/06 at90usb64/128 figure 5-7. external data memory cycles with srwn1 = 0 and srwn0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t5 is only present if the next instru ction accesses the ram (internal or external). figure 5-8. external data memory cycles with srwn1 = 1 and srwn0 = 0 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t6 is only present if the next instru ction accesses the ram (internal or external). ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 33 7593a?avr?02/06 at90usb64/128 figure 5-9. external data memory cycles with srwn1 = 1 and srwn0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t7 is only present if the next instru ction accesses the ram (internal or external). 5.5.6 external memory control register a ? xmcra ? bit 7 ? sre: external sram/xmem enable writing sre to one enables the external memory interface.the pin func tions ad7:0, a15:8, ale, wr , and rd are activated as the alternate pin functions. the sre bit overrides any pin direction settings in the respective data directio n registers. writ ing sre to zero, disables the external memory interface and the normal pin and data direction settings are used. ? bit 6..4 ? srl2:0: wait-state sector limit it is possible to configure di fferent wait-states for different external memory addresses. the external memory address space can be divided in two sectors that have separate wait-state bits. the srl2, srl1, and srl0 bits sele ct the split of the sectors, see table 5-4 and figure 5-4 . by default, the srl2, srl1, and srl0 bits are set to zero and the entire external memory address space is treated as one sector . when the entire sram address sp ace is configured as one sec- tor, the wait-states are configur ed by the srw11 and srw10 bits. ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 bit 76543210 sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 34 7593a?avr?02/06 at90usb64/128 ? bit 3..2 ? srw11, srw10: wait-s tate select bits for upper sector the srw11 and srw10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see table 5-5 . ? bit 1..0 ? srw01, srw00: wait-state select bits for lower sector the srw01 and srw00 bits control the number of wait-states for the lower sector of the exter- nal memory address space, see table 5-5 . note: 1. n = 0 or 1 (lower/upper sector). for further details of the timing and wait-states of the external memory interface, see figures 5-6 through figures 5-9 for how the setting of the srw bits affects the timing. 5.5.7 external memory control register b ? xmcrb ? bit 7? xmbk: external memory bus-keeper enable writing xmbk to one enables the bus keeper on the ad7:0 lines. when the bus keeper is enabled, ad7:0 will keep the last driven value on the lines even if the xmem interface has tri- stated the lines. writing xmbk to zero disables the bus keeper. xmbk is not qualified with sre, table 5-4. sector limits with different settings of srl2..0 srl2 srl1 srl0 sector limits 00x lower sector = n/a upper sector = 0x2100 - 0xffff 010 lower sector = 0x2100 - 0x3fff upper sector = 0x4000 - 0xffff 011 lower sector = 0x2100 - 0x5fff upper sector = 0x6000 - 0xffff 100 lower sector = 0x2100 - 0x7fff upper sector = 0x8000 - 0xffff 101 lower sector = 0x2100 - 0x9fff upper sector = 0xa000 - 0xffff 110 lower sector = 0x2100 - 0xbfff upper sector = 0xc000 - 0xffff 111 lower sector = 0x2100 - 0xdfff upper sector = 0xe000 - 0xffff table 5-5. wait states (1) srwn1 srwn0 wait states 0 0 no wait-states 0 1 wait one cycle duri ng read/write strobe 1 0 wait two cycles duri ng read/write strobe 11 wait two cycles during read/write and wait one cycle before driving out new address bit 7654 3 210 xmbk ? ? ? ? xmm2 xmm1 xmm0 xmcrb read/write r/w r r r r r/w r/w r/w initial value0000 0 000 35 7593a?avr?02/06 at90usb64/128 so even if the xmem in terface is disabled, the bus keepers ar e still activated as long as xmbk is one. ? bit 6..3 ? res: reserved bits these bits are reserved and will always read as zero. when writing to this address location, write these bits to zero for compatibility with future devices. ? bit 2..0 ? xmm2, xmm1, xmm0: external memory high mask when the external memory is enabled, all port c pins are default used for the high address byte. if the full 60kb address space is not required to a ccess the external memory, some, or all, port c pins can be released for normal port pin function as described in table 5-6 . as described in ?using all 64kb locations of external memory? on page 36 , it is possible to use the xmmn bits to access all 64kb locations of the external memory. 5.5.8 using all locations of external memory smaller than 64 kb since the external memory is mapped after the internal memory as shown in figure 5-4 , the external memory is not addressed when addres sing the first 8,448/4,352 bytes (128/64kbytes version) of data space. it may appear that the fi rst 8,448/4,352 bytes of the external memory are inaccessible (external memory addresses 0x 0000 to 0x10ff or 0x0000 to 0x20ff). however, when connecting an external memory smaller t han 64 kb, for example 32 kb, these locations are easily accessed simply by addressing from address 0x8000 to 0xa1ff. since the external memory address bit a15 is not connected to th e external memory, addresses 0x8000 to 0xa1ff will appear as addresses 0x 0000 to 0x21ff for the external me mory. addressing above address 0xa1ff is not recommended, since this will address an external memory loca tion that is already accessed by another (lower) address. to the a pplication software, the external 32 kb memory will appear as one linear 32 kb ad dress space from 0x2200 to 0x a1ff. this is illustrated in fig- ure 5-10 . table 5-6. port c pins released as normal port pi ns when the external memory is enabled xmm2 xmm1 xmm0 # bits for external memory address released port pins 0 0 0 8 (full 56kb space) none 0017 pc7 0106 pc7 - pc6 0115 pc7 - pc5 1004 pc7 - pc4 1013 pc7 - pc3 1102 pc7 - pc2 1 1 1 no address high bits full port c 36 7593a?avr?02/06 at90usb64/128 figure 5-10. address map with 32 kb external memory 5.5.9 using all 64kb locations of external memory since the external memory is mapped afte r the internal memory as shown in figure 5-4 , only 56kb of external memory is av ailable by default (address spac e 0x0000 to 0x20ff is reserved for internal memory). however, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. this can be done by using the xmmn bits and control by software the most significant bits of the addres s. by setting port c to output 0x00, and releas- ing the most significant bits for normal port pin operation, the memory interface will address 0x0000 - 0x2fff. see the following code examples. care must be exercised using this option as most of the memory is masked away. 0 x 0000 0 x 20 ff 0 x ffff 0 x 2100 0 x 7 fff 0 x 8000 0 x 0000 0 x 7 fff m e m o r y c on f i gu r a t i on a i n t e r na l m e m o r y ( u nu s ed ) av r m e m o r y m ap e xt e r na l 32 k s r a m e xt e r na l m e m o r y xmem start + 0x8000 isram end + 0x8000 xmem start isram end 37 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. assembly code example (1) ; offset is defined to 0x4000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:6 ldi r16, (1< 39 7593a?avr?02/06 at90usb64/128 6.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock al lows the asynchronous timer/c ounter to be clocked directly from an external clock or an external 32 khz cl ock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 6.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circ uitry. this gives more accurate adc conversion results. 6.1.6 usb clock ? clk usb the usb is provided with a dedicated clock domain . this clock is generated with an on-chip pll running at 48mhz. the pll always multiply its input frequency by 24. thus the pll clock regis- ter should be programmed by software to generate a 2mhz clock on the pll input. 6.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is inpu t to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 6.2.1 default clock source the device is shipped with inte rnal rc oscillator at 8.0mhz a nd with the fuse ckdiv8 pro- grammed, resulting in 1.0mhz sy stem clock. the star tup time is set to maximum and time-out period enabled. (cksel = "0010", su t = "10", ckdiv8 = "0"). the default sett ing ensures that all users can make their desired clock source se tting using any available programming interface. 6.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a mi nimum number of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. ?on-chip debug system? on page 57 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watchdog oscillator and the number of cycl es in the delay is set by the sutx and ckselx fuse bits. the selectable delays are shown in table 6-2 . the frequency of the watchdog oscillator is voltage table 6-1. device clocking options select (1) device clocking option cksel3..0 low power crystal oscillator 1111 - 1000 reserved 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128 khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 40 7593a?avr?02/06 at90usb64/128 dependent as shown in ?at90usb64/128 typical characteristics ? preliminary data? on page 429 . main purpose of the delay is to keep the avr in reset until it is supplied with minimum vcc. the delay will not monitor t he actual voltage and it will be required to select a delay longer than the vcc rise time. if this is not poss ible, an internal or external brown-out detection circuit should be used. a bod circuit will ensure sufficient vcc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay wi thout utilizing a brown-ou t detection circuit is not recommended. the oscillator is required to oscillate for a minimu m number of cycles befo re the clock is consid- ered stable. an inte rnal ripple counter monitors the oscillator output clo ck, and keeps the internal reset active for a given number of clock cycles . the reset is then released and the device will start to execute. the recommend ed oscillator start-up time is dependent on the cl ock type, and varies from 6 cycles for an externally applied clock to 32k cycles for a low frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. when starting up from power-save or power-down mode, vcc is assumed to be at a sufficient level and only the start-up time is included. 6.3 low power cr ystal oscillator pins xtal1 and xtal2 are input and output, respec tively, of an inverting amplifier which can be configured for use as an on-c hip oscillator, as shown in figure 6-2 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillator, with reduced voltage swing on the xtal2 out- put. it gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to the ?these options are intended fo r use with ceramic resonators and will ensure frequency stability at start- up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequen cy stability at start-up is not import ant for the applic ation.? on page 42 . c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the env ironment. some initial guidelines for choosing capacitors for use with crystals are given in table 6-3 . for ceramic resonators, the capacitor values given by the manufacturer should be used. table 6-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 0 ms 0 ms 0 4.1 ms 4.3 ms 512 65 ms 69 ms 8k (8,192) 41 7593a?avr?02/06 at90usb64/128 figure 6-2. crystal oscillator connections the low power oscillator c an operate in three diff erent modes, each optimi zed for a specific fre- quency range. the operating mode is selected by the fuses cksel3..1 as shown in table 6-3 . xtal 2 xtal 1 gnd c2 c1 42 7593a?avr?02/06 at90usb64/128 notes: 1. the frequency ranges are prelimin ary values. actual values are tbd. 2. this option should not be used with crystals, only with ceramic resonators. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 6-4 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. table 6-3. low power crystal osc illator operating modes (3) frequency range (1) (mhz) cksel3..1 recommended range for capacitors c1 and c2 (pf) 0.4 - 0.9 100 (2) ? 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.0 111 12 - 22 table 6-4. start-up times for the low power cr ystal oscillator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1 ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65 ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1 ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65 ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1 ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65 ms 1 11 43 7593a?avr?02/06 at90usb64/128 note: 1. the device is shipped wit h this option selected. 6.4 low frequency crystal oscillator the device can utilize a 32.768 khz watch cryst al as clock source by a dedicated low fre- quency crystal oscillator. the crystal should be connected as shown in figure 6-2 . when this oscillator is selected, start-up times are determi ned by the sut fuses and cksel0 as shown in table 6-6 . note: 1. these options should only be used if frequency stability at start-up is not important for the application. 6.5 calibrated internal rc oscillator the calibrated internal rc oscillator by default provides a 8.0 mhz clock. the frequency is nom- inal value at 3v and 25 c. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 47 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 6-7 . if selected, it will operate with no external components. during reset, hardware l oads the calibration byte into the osccal register and thereb y automatically calibrates the rc oscillator. at 3v and 25 c, this calibration gives a frequency of 8 mhz 1%. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz within 1% accuracy, by changing the osccal register. when this oscillator is used as the chip clock, the wa tchdog oscillator will still be used for the watchdog timer and for table 6-5. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (1) 10 reserved 11 table 6-6. start-up times for the lo w frequency crystal oscillator clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 bod enabled 1k ck 14ck (1) 000 fast rising power 1k ck 14ck + 4.1 ms (1) 001 slowly rising power 1k ck 14ck + 65 ms (1) 010 reserved 0 11 bod enabled 32k ck 14ck 1 00 fast rising power 32k ck 14ck + 4.1 ms 1 01 slowly rising power 32k ck 14ck + 65 ms 1 10 reserved 1 11 44 7593a?avr?02/06 at90usb64/128 the reset time-out. for more information on the pre-programmed calibration value, see the sec- tion ?calibration byte? on page 371 notes: 1. the device is shipped with this option selected. 2. the frequency ranges are preliminar y values. actual values are tbd. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. when this oscillator is select ed, start-up times are determined by the sut fuses as shown in table 6-5 on page 43 . table 6-7. internal calibrated rc o scillator operating modes (1)(3) frequency range (2) (mhz) cksel3..0 7.3 - 8.1 0010 45 7593a?avr?02/06 at90usb64/128 note: 1. the device is shipped with this option selected. 6.5.1 oscillator calibra tion register ? osccal ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration register is used to trim the calibrated inte rnal rc oscillator to remove process variations from the oscillator frequency . the factory-calibrate d value is automat- ically written to this r egister during chip reset, giving an oscillator frequen cy of 8.0 mhz at 25c. the application software can write this register to change the o scillator frequency. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz within 1% accuracy. calibration outside that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses, and these write times will be affected accordingly. if the eeprom or flash are writte n, do not calibrate to more than 8.8 mhz. other wise, the eeprom or flash write may fail. the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two fre- quency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency wi thin the selected range. a setting of 0x00 gives the lowest frequency in that range, and a se tting of 0x7f gives the highest frequency in the range. incrementing cal6..0 by 1 will give a frequency increment of less than 2% in the fre- quency range 7.3 - 8.1 mhz. 6.6 128 khz internal oscillator the 128 khz internal oscillator is a low power oscillator providing a clock of 128 khz. the fre- quency is nominal at 3v and 25 c. this clock may be select as the system clock by programming th e cksel fuses to ?11? as shown in table 6-9 . note: 1. the frequency is preliminary value. actual value is tbd. table 6-8. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (1) 10 reserved 11 bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device spec ific calibration value table 6-9. 128 khz internal osc illator operating modes nominal frequency cksel3..0 128 khz 0011 46 7593a?avr?02/06 at90usb64/128 when this clock source is select ed, start-up times are determined by the sut fuses as shown in table 6-10 . 6.7 external clock the device can utilize a external clock source as shown in figure 6-3 . to run the device on an external clock, the c ksel fuses must be programmed as shown in table 6-1 . figure 6-3. external clock drive configuration when this clock source is select ed, start-up times are determined by the sut fuses as shown in table 6-11 . when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictabl e behavior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 47 for details. table 6-10. start-up times for the 128 khz internal oscillator power conditions start-up time from power- down and power-save additional delay from reset sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4 ms 01 slowly rising power 6 ck 14ck + 64 ms 10 reserved 11 table 6-11. start-up times for the external clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms 10 reserved 11 nc external clock signal xtal2 xtal1 gnd 47 7593a?avr?02/06 at90usb64/128 6.8 clock output buffer the device can output the system clock on t he clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other cir- cuits on the system. the clock also will be output during reset, and the normal operation of i/o pin will be overridden when the fu se is programmed. any clock so urce, including the internal rc oscillator, can be selected when the clock is out put on clko. if the system clock prescaler is used, it is the divided system clock that is output. 6.9 timer/counter oscillator the device can operate its timer/counter2 from an external 32.768 khz watch crystal or a exter- nal clock source. see figure 6-2 on page 41 for crystal connection. applying an external clock source to tosc1 requi res exclk in the assr register written to logic one. see ?asynchronous operation of the timer/counter? on page 166 for further descrip- tion on selecting external clock as input instead of a 32 khz crystal. 6.10 system clock prescaler the avr usb has a system clock prescaler, and the system clock can be divided by setting the ?clock prescale register ? clkpr? on page 47 . this feature can be used to decrease the sys- tem clock frequency and the power consumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 6-12 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensu res that no intermediate frequency is higher than neither the clock frequency corresponding to th e previous setting, nor the clock frequency corre- sponding to the new setting. the ripple counter that implements the prescale r runs at the frequency of the undivided clock, which may be faster than the cpu' s clock frequency. hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cann ot be exactly predicted. from the time the clkps values are writ- ten, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired va lue to clkps while writ ing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 6.10.1 clock prescale register ? clkpr bit 7 6543210 clk- pce ???clkps 3 clkps 2 clkps 1 clkps 0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 48 7593a?avr?02/06 at90usb64/128 ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable ch ange of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously writ ten to zero. clkpce is cleared by hardware four cycles af ter it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neit her extend the time-out period, nor clear the clkpce bit. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between th e selected clock source and the internal system clock. these bits can be written run-time to va ry the clock frequency to suit the application requirements. as the divider divides the master cl ock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 6-12 . the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdi v8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. note that any value can be writt en to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. 49 7593a?avr?02/06 at90usb64/128 6.11 pll the pll is used to generate internal high frequenc y (48 mhz) clock for us b interface, the pll input is generated from an external low-frequency (the crystal oscillator or external clock input pin from xtal1). 6.11.1 internal pll for usb interface the internal pll in at90usb64/128 generates a clock frequency that is 24x multiplied from nominally 2 mhz input. the source of the 2 mhz pll input clock is the output of the internal pll clock prescaler that generates the 2 mhz (see section 6.11.2 for pll interface). table 6-12. clock prescaler select clkps3 clkps2 clk ps1 clkps0 clock di vision factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 50 7593a?avr?02/06 at90usb64/128 figure 6-4. pll clocking system 6.11.2 pll control and status register ? pllcsr ? bit 7..5 ? res: reserved bits these bits are reserved bits in the at90usb64/128 and always read as zero. ? bit 4..2 ? pllp2:0 pll prescaler these bits allow to configure the pll input pre scaler to generate the 2mhz input clock for the pll. ? bit 1 ? plle: pll enable when the plle is set, the pll is started. 8 mhz rc oscillator x tal1 x tal2 oscillators pll 24x plle lock detector plock clk usb (48mhz) pll clock prescaler system cloc k clk 2mhz oscillator watchdog bit 76543210 $29 ($29) pllp2 pllp1 pllp0 plle plock pllcsr read/writerrrrrrr/wr initial value 0 0 0 0 0 0 0/1 0 table 6-13. pll input prescaler configurations pllp2 pllp1 pllp0 clock division factor external xtal required for usb operation (mhz) 000 1 2 001 2 4 010 3 6 011 4 8 100 6 12 101 8 16 110 reserved - 111 reserved - 51 7593a?avr?02/06 at90usb64/128 ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock, and it is safe to enable pck for timer/counter1. after the pll is enabled, it takes about 100 ms for the pll to lock. 52 7593a?avr?02/06 at90usb64/128 7. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. to enter any of the five slee p modes, the se bit in smcr mu st be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power-down, power-save, or standby) will be activated by the sleep instruction. see table 7-1 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halt ed for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset oc curs during sleep mode, the mcu wakes up and executes from the reset vector. figure 6-1 on page 38 presents the different clock systems in the at90usb64/128, and their distribution. the figure is helpful in selecting an appropriate sleep mode. 7.0.1 sleep mode control register ? smcr the sleep mode control register contai ns control bits for power management. ? bits 3, 2, 1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the six available sleep modes as shown in table 7-1 . note: 1. standby modes are only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu ente r the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to writ e the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. bit 76543210 ????sm2sm1sm0sesmcr read/writerrrrr/wr/wr/wr/w initial value00000000 table 7-1. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 011power-save 100reserved 101reserved 110standby (1) 1 1 1 extended standby (1) 53 7593a?avr?02/06 at90usb64/128 7.1 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the usb, spi , usart, analog comparator, adc, 2-wire serial interface, timer/counters , watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator c ontrol and status register ? acsr. this will reduce power consumption in idle mode. if t he adc is enabled, a conver sion starts automati- cally when this mode is entered. 7.2 adc noise reduction mode when the sm2..0 bits are written to 001, t he sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowi ng the adc, the external interrupts, 2-wire serial interface address match, timer/counter2 and the watchdog to continue operating (if enabled). this sleep mode basically halts clki /o, clkcpu, and clkflash, while allowing the other clocks to run (including clkusb). this improves the noise envir onment for the adc, enabling hig her resolution measurements. if the adc is enabled, a conversion starts automati cally when this mode is entered. apart form the adc conversion complete inte rrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface interrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level interrupt on int7:4 or a pin change interrupt can wakeup the mcu from adc noise reduction mode. 7.3 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external osc illator is stopped, while the external interrupts, the 2- wire serial interface, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, 2-wire serial interface address match, an external level interrupt on int7:4, an external interrupt on int3:0, a pin change interrupt or an asynchronous usb interrupt sources (vbusti, wakeupi, id ti and hwupi), can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 95 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effectiv e. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 39 . 7.4 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power- save mode. this mode is identical to power-down, with one exception: 54 7593a?avr?02/06 at90usb64/128 if timer/counter2 is e nabled, it will keep running during sleep. the device ca n wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power- down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and asynchronously in power-save mode. if the time r/counter2 is not using t he asynchronous clock, the timer/counter oscillator is stopped during sleep. if the timer/counter2 is not using the synchronous clock, the clock source is stopped during sleep. note that even if the syn chronous clock is running in power-save, this clock is only available for the timer/counter2. 7.5 standby mode when the sm2..0 bits are 110 and an external cr ystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that th e oscillator is kept running. from standby mode, th e device wakes up in six clock cycles. 7.6 extended standby mode when the sm2..0 bits are 111 and an external cr ystal/resonator clock option is selected, the sleep instruction makes the mcu enter extended standby mode. this mode is identical to power-save mode with the exception that the oscillator is ke pt running. from extended standby mode, the device wakes up in six clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int7:4, only level interrupt. 4. asynchronous usb interrupts are vbus ti, wakeupi, idti, wakeupi and hwupi. table 7-2. active clock domains and wake-up sour ces in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc enabled int7:0 and pin change twi address match timer2 spm/ eeprom ready adc wdt interrupt other i/o usb synchronous interrupts usb asynchonous interrupts (4) idle xxxxx (2) xxxxxxxxx adcnrm x x x x (2) x (3) xx (2) xxx xx power-down x (3) xxx power-save x x (2) x (3) xxxx standby (1) xx (3) xxx extended standby x (2) xx (2) x (3) xxxx 55 7593a?avr?02/06 at90usb64/128 7.7 power reduction register the power reduction register, prr, provides a me thod to stop the clock to individual peripher- als to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the perip heral should in most cases be disabled before stopping the clock. waking up a module, whic h is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. see ?supply current of io modules? on page 429 for examples. in all other sleep modes, the clock is already stopped. 7.7.1 power reduction register 0 - prr0 ? bit 7 - prtwi: power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 - prtim2: power reduction timer/counter2 writing a logic one to this bit shuts down the timer/counter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation will cont inue like before the shutdown. ? bit 5 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, operation will cont inue like before the shutdown. ? bit 4 - res: reserved bit this bit is reserved and will always read as zero. ? bit 3 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, operation will cont inue like before the shutdown. ? bit 2 - prspi: power reductio n serial peripheral interface writing a logic one to this bit sh uts down the serial peripheral inte rface by stopping the clock to the module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - res: reserved bit these bits are reserved and will always read as zero. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts down the a dc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. bit 7654321 0 prtwi prtim2 prtim0 ? prtim1 prspi - pradc prr0 read/write r/w r/w r/w r r/w r/w r r/w initial value0000000 0 56 7593a?avr?02/06 at90usb64/128 7.7.2 power reduction register 1 - prr1 ? bit 7 - prusb: power reduction usb writing a logic one to this bit shuts down the usb by stopping the clock to the module. when waking up the usb again, the usb should be re initialized to ensure proper operation. ? bit 6..4 - res: reserved bits these bits are reserved and will always read as zero. ? bit 3 - prtim3: power reduction timer/counter3 writing a logic one to this bit shuts down the timer/counter3 module. when the timer/counter3 is enabled, operation will cont inue like before the shutdown. ? bit 2..1 - res: reserved bits these bits are reserved and will always read as zero. ? bit 0 - prusart1: power reduction usart1 writing a logic one to this bit shuts down the u sart1 by stopping the clock to the module. when waking up the usart1 again, the usart1 should be re initialized to ensure proper operation. 7.8 minimizing power consumption there are several issues to consider when tryi ng to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s func tions are operating. all functions not needed should be disabled. in parti cular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 7.8.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when th e adc is turned off and on again, the next conversion will be an exte nded conversion. refer to ?analog to digital converter - adc? on page 316 for details on adc operation. 7.8.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 313 for details on how to configure the analog comparator. bit 7 6543 210 prusb???prtim3??prusart1prr1 read/writer/wrrrr/w rrr/w initial value0 0000 000 57 7593a?avr?02/06 at90usb64/128 7.8.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always consume pow er. in the deeper sl eep modes, this will contribute sig- nificantly to the total current consumption. refer to ?brown-out detect ion? on page 60 for details on how to configure the brown-out detector. 7.8.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage refe rence will be disabled and it will not be consuming power. when turned on again, the user must allow the referenc e to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 63 for details on the start-up time. 7.8.5 watchdog timer if the watchdog timer is not neede d in the application, the module should be turn ed off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?interrupts? on page 69 for details on how to configure the watchdog timer. 7.8.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is c onsumed by the input lo gic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 77 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer s hould be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?digital input disable register 1 ? didr1? on page 315 and ?digital input dis- able register 1 ? didr1? on page 315 for details. 7.8.7 on-chip debug system if the on-chip debug system is enabled by the ocden fuse and the chip enters sleep mode, the main clock source is enabled, and hence , always consumes power. in the deeper sleep modes, this will contribute significantly to the total cu rrent consumption. there are three alte rnative ways to disable the ocd system: ? disable the ocden fuse. ? disable the jtagen fuse. ? write one to the jtd bit in mcucr. 58 7593a?avr?02/06 at90usb64/128 8. system control and reset 8.0.1 resetting the avr during reset, all i/o registers are set to their initial values, and the pr ogram starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the app lication section wh ile the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 8-1 shows the reset logic. table 8-1 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 39 . 8.0.2 reset sources the at90usb64/128 has five sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is pr esent on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as th ere is a logic one in the reset register, one of the scan chains of the jtag system. refer to the section ?ieee 1149.1 (jtag) boundary- scan? on page 341 for details. 59 7593a?avr?02/06 at90usb64/128 figure 8-1. reset logic notes: 1. values are guidelines only. actual values are tbd. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling) 8.0.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 8-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up re set, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. table 8-1. reset characteristics (1) symbol parameter condition min typ max units v pot power-on reset threshold voltage (rising) tbd tbd tbd v power-on reset threshold voltage (falling) (2) tbd tbd tbd v v rst reset pin threshold voltage tbd tbd tbd v t rst minimum pulse width on reset pin tbd tbd tbd ns mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor jtrf jtag reset register watchdog oscillator sut[1:0] power-on reset circuit 60 7593a?avr?02/06 at90usb64/128 figure 8-2. mcu start-up, reset tied to v cc figure 8-3. mcu start-up, reset extended externally 8.0.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 8-1 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 8-4. external reset during operation 8.0.5 brown-out detection at90usb64/128 has an on-chip brown-out dete ction (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be v reset time-out i nternal reset t tout v pot v rst cc reset time-out i nternal reset t tout v pot v rst v cc cc 61 7593a?avr?02/06 at90usb64/128 selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longe r guaranteed. the test is performed using bodlevel = 110 for at90usb64/128 and bodlevel = 101 for at90usb64/128l. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 8-5 ), the brown-out reset is i mmediately activated. when v cc increases above the trigger level (v bot+ in figure 8-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 8-1 . figure 8-5. brown-out reset during operation table 8-2. bodlevel fuse coding (1) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 2.0 v 101 2.2 100 2.4 011 2.6 010 3.4 001 3.5 000 4.3 table 8-3. brown-out characteristics symbol parameter min typ max units v hyst brown-out detector hysteresis 50 mv t bod min pulse width on brown-out reset ns v cc reset time-out i nternal reset v bot- v bot+ t tout 62 7593a?avr?02/06 at90usb64/128 8.0.6 watchdog reset when the watchdog times out, it will generate a short reset pu lse of one ck cycle duration. on the falling edge of this pulse, the delay ti mer starts counting the time-out period t tout . refer to page 63 for details on operation of the watchdog timer. figure 8-6. watchdog reset du ring operation 8.0.7 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is rese t by a power-on reset, or by writing a logic zero to the flag. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog re set occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the pr ogram. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. ck cc bit 76543210 ? ? ? jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 63 7593a?avr?02/06 at90usb64/128 8.1 internal voltage reference at90usb64/128 features an internal bandgap reference. this reference is used for brown-out detection, and it can be used as an inpu t to the analog comparator or the adc. 8.1.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 8-4 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. note: 1. values are guidelines only. actual values are tbd. 8.2 watchdog timer at90usb64/128 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separat e on-chip oscillator ? 3 operating modes ?interrupt ? system reset ? interrupt and system reset table 8-4. internal voltage reference characteristics (1) symbol parameter condi tion min typ max units v bg bandgap reference voltage tbd tbd 1.1 tbd v t bg bandgap reference start-up time tbd 40 70 s i bg bandgap reference current consumption tbd 10 tbd a 64 7593a?avr?02/06 at90usb64/128 ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode figure 8-7. watchdog timer the watchdog timer (wdt) is a timer counting cycles of a separa te on-chip 128 khz oscillator. the wdt gives an interrupt or a system reset wh en the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the count er before the time-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain opera tions, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent sys tem hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an inter- rupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. the watchdog always on (wdton ) fuse, if programmed, will forc e the watchdog timer to sys- tem reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respective ly. to further ensure program security, alter- ations to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out conf iguration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt 65 7593a?avr?02/06 at90usb64/128 the following code example shows one assembly and one c function for turning off the watch- dog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during th e execution of these functions. note: 1. the example code assumes that the part specific header file is included. note: if the watchdog is accidental ly enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should a lways clear the watchdog system reset flag (wdrf) and the wde control bit in the initialisatio n routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 68 7593a?avr?02/06 at90usb64/128 . table 8-6. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 69 7593a?avr?02/06 at90usb64/128 9. interrupts this section describes the specifics of the interrupt handling as performed in at90usb64/128. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 15 . 9.1 interrupt vectors in at90usb64/128 table 9-1. reset and interrupt vectors vector no. program address (2) source interrup t definition 1 $0000 (1) reset external pin, power-on reset, brown-out reset, watchdog reset, and jtag avr reset 2 $0002 int0 external interrupt request 0 3 $0004 int1 external interrupt request 1 4 $0006 int2 external interrupt request 2 5 $0008 int3 external interrupt request 3 6 $000a int4 external interrupt request 4 7 $000c int5 external interrupt request 5 8 $000e int6 external interrupt request 6 9 $0010 int7 external interrupt request 7 10 $0012 pcint0 pin change interrupt request 0 11 $0014 usb general usb general interrupt request 12 $0016 usb endpoint/pipe usb endpoint/pipe interrupt request 13 $0018 wdt watchdog time-out interrupt 14 $001a timer2 compa timer/counter2 compare match a 15 $001c timer2 compb timer/counter2 compare match b 16 $001e timer2 ovf timer/counter2 overflow 17 $0020 timer1 capt timer/counter1 capture event 18 $0022 timer1 compa timer/counter1 compare match a 19 $0024 timer1 compb timer/counter1 compare match b 20 $0026 timer1 compc timer/counter1 compare match c 21 $0028 timer1 ovf timer/counter1 overflow 22 $002a timer0 compa timer/counter0 compare match a 23 $002c timer0 compb timer/counter0 compare match b 24 $002e timer0 ovf timer/counter0 overflow 25 $0030 spi, stc spi serial transfer complete 26 $0032 usart1 rx usart1 rx complete 27 $0034 usart1 udre usart1 data register empty 28 $0036 usart1tx usart1 tx complete 70 7593a?avr?02/06 at90usb64/128 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?memory programming? on page 368 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be mo ved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 9-2 shows reset and interrupt vectors placem ent for the various combinations of bootrst and ivsel settings. if the program never enables an in terrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the applicat ion section while the interrupt vectors are in the boot section or vice versa. 29 $0038 analog comp analog comparator 30 $003a adc adc conversion complete 31 $003c ee ready eeprom ready 32 $003e timer3 capt timer/counter3 capture event 33 $0040 timer3 compa timer/counter3 compare match a 34 $0042 timer3 compb timer/counter3 compare match b 35 $0044 timer3 compc timer/counter3 compare match c 36 $0046 timer3 ovf timer/counter3 overflow 37 $0048 twi 2-wire serial interface 38 $004a spm ready store program memory ready table 9-1. reset and interrupt vectors (continued) vector no. program address (2) source interrup t definition 71 7593a?avr?02/06 at90usb64/128 note: 1. the boot reset address is shown in table 28-8 on page 366 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. 9.1.1 moving interrupts between application and boot space the general interrupt control register controls the placement of the interrupt vector table. 9.1.2 mcu control register ? mcucr ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are pl aced at the start of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to the section ?memory programming? on page 368 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired valu e to ivsel while writ ing a zero to ivce. interrupts will automatically be di sabled while this sequence is ex ecuted. interrupts are disabled in the cycle ivce is set, and they remain disabl ed until after the instruct ion following the write to ivsel. if ivsel is not written, interrupts remain di sabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing fr om the application section. if interrupt vectors are placed in the application section and boot lo ck bit blb12 is programed, interrupts are dis- abled while executing from the boot loader section. refer to the section ?memory programming? on page 368 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable table 9-2. reset and interrupt vectors placement (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 72 7593a?avr?02/06 at90usb64/128 the ivce bit must be written to logic one to enable change of th e ivsel bit. ivce is cleared by hardware four cyc les after it is written or when ivsel is written. sett ing the ivce bit will disable interrupts, as explained in the ivsel description above. see code example below. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 74 7593a?avr?02/06 at90usb64/128 note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. 10.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 10-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 10-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 10.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o-ports? on page 91 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero , pxn is configured as an input pin. if portxn is written logic one w hen the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up re sistor off, portxn has to be wri tten logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 75 7593a?avr?02/06 at90usb64/128 if portxn is written logic one when the pin is configured as an outp ut pin, the port pin is driven high (one). if portxn is writte n logic zero when the pin is config ured as an output pin, the port pin is driven low (zero). 10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be us ed to toggle one single bit in a port. 10.2.3 switching between input and output when switching between tri-state ({ddxn, port xn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) occurs . normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the di fference between a strong high driver and a pull-up. if this is not the case, the pud bit in th e mcucr register can be set to disable all pull- ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 10-1 summarizes the control signals for the pin value. 10.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 10-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 10-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 10-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 76 7593a?avr?02/06 at90usb64/128 figure 10-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 10-4 . the out instruction sets the ?sync latch? signal at t he positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 10-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups as signed to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 77 7593a?avr?02/06 at90usb64/128 note: 1. for the assembly program, two temporary re gisters are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the di rection bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 10.2.5 digital input enable and sleep modes as shown in figure 10-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denot ed sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as exte rnal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pi ns. sleep is also over ridden by various other alternate functions as described in ?alternate port functions? on page 78 . if a logic high level (?one?) is present on an asyn chronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 unconnected pins if some pins are unused, it is recommended to ensure that these pi ns have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, float- assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 79 7593a?avr?02/06 at90usb64/128 table 10-2 summarizes the function of the overriding signals. the pin and port indexes from fig- ure 10-5 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alte rnate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 10-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the outp ut driver enable is controlled by the ddov signal. if this si gnal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port val ue is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 80 7593a?avr?02/06 at90usb64/128 10.3.1 mcu control register ? mcucr ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 74 for more details about this feature. 10.3.2 alternate functions of port a the port a has an alternate function as the address low byte and data lines for the external memory interface. table 10-4 and table 10-5 relates the alternate functions of port a to the overriding signals shown in figure 10-5 on page 78 . bit 7 6 5 4 3 2 1 0 jtd ? ?pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 10-3. port a pins alternate functions port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0) table 10-4. overriding signals for alternate functions in pa7..pa4 signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre sre sre sre puov ~(wr | ada (1) ) ? porta7 ? pud ~(wr | ada) ? porta6 ? pud ~(wr | ada) ? porta5 ? pud ~(wr | ada) ? porta4 ? pud ddoe sre sre sre sre ddov wr | ada wr | ada wr | ada wr | ada pvoe sre sre sre sre pvov a7 ? ada | d7 output ? wr a6 ? ada | d6 output ? wr a5 ? ada | d5 output ? wr a4 ? ada | d4 output ? wr dieoe 0 0 0 0 dieov 0 0 0 0 did7 inputd6 inputd5 inputd4 input aio ? ? ? ? 81 7593a?avr?02/06 at90usb64/128 note: 1. ada is short for address active and represents the time when address is output. see ?exter- nal memory interface? on page 29 for details. 10.3.3 alternate functions of port b the port b pins with altern ate functions are shown in table 10-6 . the alternate pin configuration is as follows: ? oc0a/oc1c/pcint7, bit 7 oc0a, output compare match a output: the pb7 pi n can serve as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a pin is also th e output pin for the pwm mode timer function. table 10-5. overriding signals for alternate functions in pa3..pa0 signal name pa3/ad3 pa2/ad2 pa1/ad1 pa0/ad0 puoe sre sre sre sre puov ~(wr | ada) ? porta3 ? pud ~(wr | ada) ? porta2 ? pud ~(wr | ada) ? porta1 ? pud ~(wr | ada) ? porta0 ? pud ddoe sre sre sre sre ddov wr | ada wr | ada wr | ada wr | ada pvoe sre sre sre sre pvov a3 ? ada | d3 output ? wr a2? ada | d2 output ? wr a1 ? ada | d1 output ? wr a0 ? ada | d0 output ? wr dieoe 0 0 0 0 dieov 0 0 0 0 di d3 input d2 input d1 input d0 input aio ? ? ? ? table 10-6. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c/pcint7 (output compare and pwm output a for timer/counter0, output compare and pwm output c for timer/counter1 or pin change interrupt 7) pb6 oc1b/pcint6 (output compare and pwm ou tput b for timer/counter1 or pin change interrupt 6) pb5 oc1a/pcint5 (output compare and pwm ou tput a for timer/counter1 or pin change interrupt 5) pb4 oc2a/pcint4 (output compare and pwm ou tput a for timer/counter2 or pin change interrupt 4) pb3 pdo/miso/pcint3 (programmi ng data output or spi bus master input/slave output or pin change interrupt 3) pb2 pdi/mosi/pcint2 (programmi ng data input orspi bus master output/slave input or pin change interrupt 2) pb1 sck/pcint1 (spi bus serial clock or pin change interrupt 1) pb0 ss /pcint0 (spi slave select input or pin change interrupt 0) 82 7593a?avr?02/06 at90usb64/128 oc1c, output compare match c output: the pb7 pi n can serve as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set (one)) to serve this function. the oc1c pin is also the output pin for the pwm mode timer function. pcint7, pin change interrupt source 7: the pb7 pin can serve as an external interrupt source. ? oc1b/pcint6, bit 6 oc1b, output compare match b output: the pb6 pi n can serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. pcint6, pin change interrupt source 6: the pb7 pin can serve as an external interrupt source. ? oc1a/pcint5, bit 5 oc1a, output compare match a output: the pb5 pi n can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set (one)) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint5, pin change interrupt source 5: the pb7 pin can serve as an external interrupt source. ? oc2a/pcint4, bit 4 oc2a, output compare match output: the pb4 pin can serve as an external output for the timer/counter2 output compare. the pin has to be configured as an output (ddb4 set (one)) to serve this function. the oc2a pin is also th e output pin for the pwm mode timer function. pcint4, pin change interrupt source 4: the pb7 pin can serve as an external interrupt source. ? pdo/miso/pcint3 ? port b, bit 3 pdo, spi serial programming data output. during serial program downloading, this pin is used as data output line for the at90usb64/128. miso: master data input, slave data output pi n for spi channel. when the spi is enabled as a master, this pin is configured as an input regar dless of the setting of ddb3. when the spi is enabled as a slave, the data direction of this pi n is controlled by ddb3. when the pin is forced to be an input, the pull- up can still be controlled by the portb3 bit. pcint3, pin change interrupt source 3: the pb7 pin can serve as an external interrupt source. ? pdi/mosi/pcint2 ? port b, bit 2 pdi, spi serial programming data input. during serial program downloading, this pin is used as data input line for the at90usb64/128. mosi: spi master data output, sl ave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regar dless of the setting of ddb2. when the spi is enabled as a master, the data direct ion of this pin is controlled by ddb2. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb2 bit. pcint2, pin change interrupt source 2: the pb7 pin can serve as an external interrupt source. ? sck/pcint1 ? po rt b, bit 1 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb1. when the spi0 is enabled as a master, the data direct ion of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb1 bit. 83 7593a?avr?02/06 at90usb64/128 pcint1, pin change interrupt source 1: the pb7 pin can serve as an external interrupt source. ?ss /pcint0 ? port b, bit 0 ss : slave port select input. when the spi is enab led as a slave, this pi n is configured as an input regardless of the setting of ddb0. as a slav e, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data di rection of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 bit. table 10-7 and table 10-8 relate the alternate functions of port b to the overriding signals shown in figure 10-5 on page 78 . spi mstr input and spi sl ave output constitute the miso signal, while mosi is divided in to spi mstr output and spi slave input. pcint0, pin change interrupt source 0: the pb7 pin can serve as an external interrupt source.. table 10-7. overriding signals for alternate functions in pb7..pb4 signal name pb7/pcint7/oc0a/ oc1c pb6/pcint6/oc 1b pb5/pcint5/oc 1a pb4/pcint4/oc 2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0/oc1c enable oc1b enabl e oc1a enable oc2a enable pvov oc0/oc1c oc1b oc1a oc2a dieoe pcint7 ? pcie0 pcint6 ? pcie0 pcint5 ? pcie0 pcint4 ? pcie0 dieov 1 1 1 1 di pcint7 input pcint6 inpu t pcint5 input pcint4 input aio ? ? ? ? table 10-8. overriding signals for alternate functions in pb3..pb0 signal name pb3/pd0/pcint3/ miso pb2/pdi/pcint2/ mosi pb1/pcint1/ sck pb0/pcint0/ ss puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi mstr output sck output 0 dieoe pcint3 ? pcie0 pcint2 ? pcie0 pcint1 ? pcie0 pcint0 ? pcie0 dieov 1 1 1 1 di spi mstr input pcint3 input spi slave input pcint2 input sck input pcint1 input spi ss pcint0 input aio ? ? ? ? 84 7593a?avr?02/06 at90usb64/128 10.3.4 alternate functions of port c the port c alternate function is as follows: table 10-10 and table 10-11 relate the alternate functions of port c to the overriding signals shown in figure 10-5 on page 78 . table 10-9. port c pins alternate functions port pin alternate function pc7 a15/ic.3/clko(external memory interface address bit 15 or input capture timer 3 or clk0 (divided system clock) pc6 a14/oc.3a(external memory interface address bit 14 or output compare and pwm output a for timer/counter3) pc5 a13/oc.3b(external memory interface address bit 13 or output compare and pwm output b for timer/counter3) pc4 a12/oc.3c(external memory interface address bit 12 or output compare and pwm output c for timer/counter3) pc3 a11/t.3(external memory interface address bit 11or timer/counter3 clok input) pc2 a10(external memory interface address bit 10) pc1 a9(external memory interface address bit 9) pc0 a8(external memory interface address bit 8) table 10-10. overriding signals for alternate functions in pc7..pc4 signal name pc7/a15/ic.3/clk o pc6/a14/oc.3a pc5/a 13/oc.3b pc4/a12/oc.3c puoe sre ? (xmm<1) sre ? (xmm<2)|oc3a enable sre ? (xmm<3)|oc3b enable sre ? (xmm<4)|oc3c enable puov 0 0 0 0 ddoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) ddov 1 1 1 1 pvoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) pvov a15 if (sre.xmm<2) then a14 else oc3a if (sre.xmm<2) then a13 else oc3b if (sre.xmm<2) then a12 else oc3c dieoe 0 0 0 0 dieov 0 0 0 0 di icp3 input ? ? ? aio ? ? ? ? 85 7593a?avr?02/06 at90usb64/128 10.3.5 alternate functions of port d the port d pins with alternate functions are shown in table 10-12 . the alternate pin configuration is as follows: ? t0 ? port d, bit 7 t0, timer/counter0 counter source. ? t1 ? port d, bit 6 t1, timer/counter1 counter source. ? xck1 ? port d, bit 5 xck1, usart1 external clock. th e data direction register (ddd5) controls whether the clock is output (ddd5 set) or input (ddd5 cleared). the xck1 pin is active only when the usart1 operates in synchronous mode. table 10-11. overriding signals for alternate functions in pc3..pc0 signal name pc3/a11/t.3 pc2/a10 pc1/a9 pc0/a8 puoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) puov0000 ddoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) ddov 1 1 1 1 pvoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) pvov a11 a10 a9 a8 dieoe0000 dieov0000 di t3 input ? ? ? aio???? table 10-12. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 t1 (timer/counter1 clock input) pd5 xck1 (usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 int3 /txd1 (external interrupt3 input or usart1 transmit pin) pd2 int2/rxd1 (external interrupt2 input or usart1 receive pin) pd1 int1 /sda/oc2b (external interrupt1 input or twi serial data or output compare for timer/counter2) pd0 int0 /scl/oc0b (external interrupt0 input or twi serial clock or output compare for timer/counter0) 86 7593a?avr?02/06 at90usb64/128 ? icp1 ? port d, bit 4 icp1 ? input capture pin 1: the pd4 pin can ac t as an input capture pin for timer/counter1. ?int3 /txd1 ? port d, bit 3 int3, external interrupt source 3: the pd3 pin c an serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1). when the usart1 transmitter is enabled, this pin is configured as an output regardless of the value of ddd3. ?int2 /rxd1 ? port d, bit 2 int2, external interrupt source 2. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the u sart1). when the usart1 receiver is enabled this pin is configured as an input regardless of the value of ddd2. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. ?int1 /sda/oc2b ? port d, bit 1 int1, external interrupt source 1. the pd1 pin c an serve as an external interrupt source to the mcu. sda, 2-wire serial interface data: when the twen bit in twcr is set (one ) to enable the 2-wire serial interface, pin pd1 is disconnected from t he port and becomes the serial data i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew- rate limitation. ?int0 /scl/oc0b ? port d, bit 0 int0, external interrupt source 0. the pd0 pin c an serve as an external interrupt source to the mcu. scl, 2-wire serial interface clock: when the tw en bit in twcr is set (one) to enable the 2- wire serial interface, pin pd 0 is disconnected from the port and becomes the serial clock i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driv en by an open drain driver with slew-rate limitation. table 10-13 and table 10-14 relates the alternate functions of port d to the overriding signals shown in figure 10-5 on page 78 . 87 7593a?avr?02/06 at90usb64/128 note: 1. when enabled, the 2-wire serial interface en ables slew-rate controls on the output pins pd0 and pd1. this is not shown in this table. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. table 10-13. overriding signals for alternate functions pd7..pd4 signal name pd7/t0 pd 6/t1 pd5/xck1 pd4/icp1 puoe000 0 puov000 0 ddoe 0 0 xck1 output enable 0 ddov 0 0 1 0 pvoe 0 0 xck1 output enable 0 pvov 0 0 xck1 output 0 dieoe000 0 dieov000 0 di t0 input t1 input xck1 input icp1 input aio??? ? table 10-14. overriding signals for alternate functions in pd3..pd0 (1) signal name pd3/int3 /txd1 pd2/int2/rxd1 pd1/int1/sda/ oc2b pd0/int0/scl/ oc0b puoe txen1 rxen1 twen twen puov 0 portd2 ? pud portd1 ? pud portd0 ? pud ddoe txen1 rxen1 twen twen ddov 1 0 sda_out scl_out pvoe txen1 0 twen | oc2b enable twen | oc0b enable pvov txd1 0 oc2b oc0b dieoe int3 enable int2 enable int1 enable int0 enable dieov 1 1 1 1 di int3 input int2 input/rxd1 int1 input int0 input aio ? ? sda input scl input 88 7593a?avr?02/06 at90usb64/128 10.3.6 alternate functions of port e the port e pins with altern ate functions are shown in table 10-15 . ? int7/ain.1/uvcon ? port e, bit 7 int7, external interrup t source 7: the pe7 pin can serve as an external interrupt source. ain1 ? analog comparator negative input. this pi n is directly connected to the negative input of the analog comparator. uvcon - when using usb host mode, this pin allows to control an external vbus generator (active high). ? int6/ain.0 ? port e, bit 6 int6, external interrup t source 6: the pe6 pin can serve as an external interrupt source. ain0 ? analog comparator negative input. this pi n is directly connected to the negative input of the analog comparator. ? int5/tosc2 ? port e, bit 5 int5, external interrup t source 5: the pe5 pin can serve as an external interrupt source. tosc2, timer/counter2 oscillator pin1. when th e as2 bit in assr is set to enable asynchro- nous clocking of timer/counter2, pin pe5 is di sconnected from the port, and becomes the ouput of the inverting oscillator amplifier. in this mode , a crystal is connected to this pin, and the pin can not be used as an i/o pin. ? int4/tosc1 ? port e, bit 4 int4, external interrup t source 4: the pe4 pin can serve as an external interrupt source. tosc1, timer/counter2 oscillator pin2. when th e as2 bit in assr is set to enable asynchro- nous clocking of timer/counter2, pin pe4 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. in this mode , a crystal is connected to this pin, and the pin can not be used as an i/o pin. ? uid ? port e, bit 3 id pin of the usb bus. ? ale/hwb ? port e, bit 2 table 10-15. port e pins alternate functions port pin alternate function pe7 int7/ain.1/uvcon (external interrupt 7 input, analog comparator positive input or vbus control) pe6 int6/ain.0 (external interrupt 6 input or analog comparator positive input) pe5 int5/tosc2 (external interrupt 5 inpu t or rtc oscillator timer/counter2)) pe4 int4/tosc2 (external interrupt4 input or rtc oscillator timer/counter2) pe3 uid pe2 ale/hwb (address latch to extenal memo ry or hardware bootloader activation) pe1 rd (read strobe to external memory) pe0 wr (write strobe to external memory) 89 7593a?avr?02/06 at90usb64/128 ale is the external data memory address latch enable. hwb allows to execute the bootloader section after reset when tied to ground during external reset pulse. the hwb mode of this pin is ac tive only when the hwbe fuse is enable. ?rd ? port e, bit 1 rd is the external data memory read control enable. ?wr ? port e, bit 0 wr is the external data memory write control enable. table 10-16. overriding signals for alternate functions pe7..pe4 signal name pe7/int7/ain.1/ uvcon pe6/int6/ain.0 pe5/int5/ tosc1 pe4/int4/ tosc2 puoe 0 0 0 0 puov 0 0 0 0 ddoe uvcone 0 0 0 ddov uvcone 0 0 0 pvoe uvcone 0 0 0 pvov uvcon 0 0 0 dieoe int7 enable int6 enabl e int5 enable int4 enable dieov 1 1 1 1 di int7 input int6 input int5 input int4 input aio ain1 input ain0 input ? ? table 10-17. overriding signals for alternate functions in pe3..pe0 signal name pe3/uid pe2 /ale/hwb pe1/rd pe0/wr puoe uide 0 sre sre puov 1 0 0 0 ddoe uide sre sre sre ddov 0 1 1 0 pvoe 0 sre sre sre pvov 0 ale rd wr dieoe uide 0 0 0 dieov 1 0 0 1 di uid hwb ? ? pe0 0 0 0 0 aio ? ? ? ? 90 7593a?avr?02/06 at90usb64/128 10.3.7 alternate functions of port f the port f has an alternate function as analog input for the adc as shown in table 10-18 . if some port f pins are configured as outputs, it is essential that these do not switch when a con- version is in progress. this might corrupt the re sult of the conversion. if the jtag interface is enabled, the pull-up resi stors on pins pf7(tdi) , pf5(tms), and pf4(tck) will be activated even if a reset occurs. ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, channel 7 . tdi, jtag test data in: serial input data to be sh ifted in to the instruction register or data reg- ister (scan chains). when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tdo, adc6 ? port f, bit 6 adc6, analog to digital converter, channel 6 . tdo, jtag test data out: serial output data fr om instruction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. the tdo pin is tri-stated unless tap st ates that shift out data are entered. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, channel 5 . tms, jtag test mode select: this pin is used for navigating through the tap-controller state machine. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tck, adc4 ? port f, bit 4 adc4, analog to digital converter, channel 4 . tck, jtag test clock: jtag operation is synchronous to tck. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? adc3 ? adc0 ? port f, bit 3..0 table 10-18. port f pins alternate functions port pin alter nate function pf7 adc7/tdi (adc input channel 7 or jtag test data input) pf6 adc6/tdo (adc input channel 6 or jtag test data output) pf5 adc5/tms (adc input channel 5 or jtag test mode select) pf4 adc4/tck (adc input channel 4 or jtag test clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 91 7593a?avr?02/06 at90usb64/128 analog to digital converter, channel 3..0. 10.4 register description for i/o-ports 10.4.1 port a data register ? porta table 10-19. overriding signals for alternate functions in pf7..pf4 signal name pf7/adc7/tdi pf6/adc6/td o pf5/adc5/tms pf4/adc4/tck puoe jtagen jtagen jtagen jtagen puov 1 0 1 1 ddoe jtagen jtagen jtagen jtagen ddov 0 shift_ir + shift_dr 00 pvoe 0 jtagen 0 0 pvov 0 tdo 0 0 dieoe jtagen jtagen jtagen jtagen dieov 0 0 0 0 di ? ? ? ? aio tdi/adc7 input adc6 input tms/adc5 input tck/adc4 input table 10-20. overriding signals for alternate functions in pf3..pf0 signal name pf3/adc3 pf 2/adc2 pf1/adc1 pf0/adc0 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di???? aio adc3 input adc2 input adc1 input adc0 input bit 76543210 porta 7 porta 6 porta 5 porta 4 porta 3 porta 2 porta 1 porta 0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 92 7593a?avr?02/06 at90usb64/128 10.4.2 port a data di rection register ? ddra 10.4.3 port a input pins address ? pina 10.4.4 port b data register ? portb 10.4.5 port b data di rection register ? ddrb 10.4.6 port b input pins address ? pinb 10.4.7 port c data register ? portc 10.4.8 port c data di rection register ? ddrc 10.4.9 port c input pins address ? pinc bit 76543210 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portb 7 portb 6 portb 5 portb 4 portb 3 portb 2 portb 1 portb 0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portc 7 portc 6 portc 5 portc 4 portc 3 portc 2 portc 1 portc 0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinc7 pinc6 pinc5 pinc4 pi nc3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 93 7593a?avr?02/06 at90usb64/128 10.4.10 port d data register ? portd 10.4.11 port d data direction register ? ddrd 10.4.12 port d input pins address ? pind 10.4.13 port e data register ? porte 10.4.14 port e data dire ction register ? ddre 10.4.15 port e input pins address ? pine 10.4.16 port f data register ? portf 10.4.17 port f data direction register ? ddrf bit 76543210 portd 7 portd 6 portd 5 portd 4 portd 3 portd 2 portd 1 portd 0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 porte 7 porte 6 porte 5 porte 4 porte 3 porte 2 porte 1 porte 0 porte read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portf 7 portf 6 portf 5 portf 4 portf 3 portf 2 portf 1 portf 0 portf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 94 7593a?avr?02/06 at90usb64/128 10.4.18 port f input pins address ? pinf bit 76543210 pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 95 7593a?avr?02/06 at90usb64/128 11. external interrupts the external interrupts are triggered by the int7 :0 pin or any of the pcint23..0 pins. observe that, if enabled, the inte rrupts will trigger even if the int7:0 or pcint23..0 pins are configured as outputs. this feature provides a wa y of generating a software interrupt. the pin change interrupt pci0 will trigger if an y enabled pcint7:0 pin toggles. pcmsk0 regis- ter control which pins contribute to the pin change interrupts. pin change interrupts on pcint7 ..0 are detected asynchronously. this implies that these interrupts ca n be used for waking the part also from sleep modes other than idle mode. the external interrupts can be triggered by a falli ng or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control registers ? eicra (int3:0) and eicrb (int7:4). when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int7:4 requires the presence of an i/o clock, described in ?system clock and clock options? on page 38 . low level interrupts and the edge interrupt on int3:0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete t he wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the start- up time is defined by the su t and cksel fuses as described in ?system clock and clock options? on page 38 . 11.0.1 external interrupt control register a ? eicra the external interrupt control register a cont ains control bits for interrupt sense control. ? bits 7..0 ? isc31, isc30 ? isc00, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 11-1 . edges on int3..int0 are registered asynchro- nously. pulses on int3:0 pins wider than the minimum pulse width given in table 11-2 will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an inter- rupt request as long as the pin is held low. wh en changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by writing a logical one to its interrupt flag bit (intfn) in the eifr register before the interrupt is re-enabled. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 96 7593a?avr?02/06 at90usb64/128 note: 1. n = 3, 2, 1or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 11.0.2 external interrupt control register b ? eicrb ? bits 7..0 ? isc71, isc70 - isc41, isc40: external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are activated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 11-3 . the value on the int7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an inter- rupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is select ed, the low level must be held until the comple- tion of the currently ex ecuting instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. note: 1. n = 7, 6, 5 or 4. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 11.0.3 external interrupt mask register ? eimsk table 11-1. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any edge of intn generates asynchronously an interrupt request. 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. table 11-2. asynchronous external interrupt characteristics symbol parameter condi tion min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns bit 76543210 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 11-3. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request 10 the falling edge between two samples of intn generates an interrupt request. 11 the rising edge between two samples of intn generates an interrupt request. bit 76543210 97 7593a?avr?02/06 at90usb64/128 ? bits 7..0 ? int7 ? int0: external interrupt request 7 - 0 enable when an int7 ? int0 bit is written to one and t he i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ? eicra an d eicrb ? defines whethe r the external inter- rupt is activated on risi ng or falling edge or level sensed. acti vity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 11.0.4 external interrupt flag register ? eifr ? bits 7..0 ? intf7 - intf0: external interrupt flags 7 - 0 when an edge or logic change on the int7:0 pin triggers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the corresp onding interrupt enable bit, int7:0 in eimsk, are set (one), the mcu will jump to the interrupt vector . the flag is cleared wh en the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int7:0 are configured as level interrupt. note that when entering sleep mode with the int3:0 interrupts disabled, the input buffers on these pins will be disabled. this may cause a logic change in internal si gnals which will set the intf3:0 flags. see ?digital input enable and sleep modes? on page 77 for more information. 11.0.5 pin change interrupt control register - pcicr ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one) , pin change interrupt 0 is enabled. any change on any enabled pcint7..0 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector . pcint7..0 pins are enabled indi vidually by the pcmsk0 register. 11.0.6 pin change interrupt flag register ? pcifr ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint7..0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and t he pcie0 bit in eimsk are set ( one), the mcu will jump to the int7 int6 int5 int4 int3 int2 int1 iint0 eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? ? ? ?pcie0pcicr read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? ? ? ? ?pcif0pcifr read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0 98 7593a?avr?02/06 at90usb64/128 corresponding interrupt vector. the flag is cleared when the interrupt rout ine is executed. alter- natively, the flag can be cleared by writing a logical one to it. 11.0.7 pin change mask register 0 ? pcmsk0 ? bit 7..0 ? pcint7..0: pin change enable mask 7..0 each pcint7..0 bit selects whet her pin change interrupt is e nabled on the co rresponding i/o pin. if pcint7..0 is set and the pcie0 bit in pci cr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7 ..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 99 7593a?avr?02/06 at90usb64/128 12. timer/counter0, timer/counter1, and timer/counter3 prescalers timer/counter0, 1, and 3 share the same presca ler module, but the time r/counters can have different prescaler settings. the description below a pplies to all timer/counte rs. tn is used as a general name, n = 0, 1 or 3. 12.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 12.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by the timer/counter tn. since t he prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will ha ve implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occu rs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. however, care must be taken if the othe r timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for a ll timer/counters it is connected to. 12.3 external clock source an external clock source applied to the tn pin can be used as ti mer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by the pin synchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 1 shows a functional equivalent block diagram of the tn synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk tn pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 1. tn/t0 pin sampling the synchronization and e dge detector logic introduces a dela y of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn pin to the counter is updated. enabling and disabling of the clock input must be done when tn has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 100 7593a?avr?02/06 at90usb64/128 each half period of the exter nal clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 2. prescaler for synchronous timer/counters 12.4 general timer/counter control register ? gtccr ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activa tes the timer/counter synchroniz ation mode. in this mode, the value that is written to the psrasy and psrsync bits is kept , hence keeping the correspond- ing prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. wh en the tsm bit is written to zero, the psrasy and psrsync bits are cleared by hardware, and the timer/counte rs start counting simultaneously. ? bit 0 ? psrsync: prescaler reset for synchronous timer/counters when this bit is one, timer/counter0 and time r/counter1, timer/counter3, timer/counter4 and timer/counter5 prescaler will be re set. this bit is normally clea red immediately by hardware, except if the tsm bit is set. note that ti mer/counter0, timer/counter1, timer/counter3, timer/counter4 and timer/counte r5 share the same prescaler and a reset of this prescaler will affect all timers. psr10 clear tn tn clk i/o synchronization synchronization timer/countern clock source clk tn timer/countern clock source clk tn csn0 csn1 csn2 csn0 csn1 csn2 bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psra- sy psrsy nc gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 101 7593a?avr?02/06 at90usb64/128 13. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bit time r/counter module, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event man- agement) and wave generation. the main features are: ? two independent output compare units ? double buffered output compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 13.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 13-1 . for the actual placement of i/o pins, refer to ?pinout at90usb64/128-tqfp? on page 3 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bo ld. the device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 111 . figure 13-1. 8-bit timer/counter block diagram 13.1.1 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req . in the figure) signals are all visible in the timer interrupt flag register (t ifr0). all interrupts are individually masked with the timer inter- rupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block contro ls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from th e clock select logic is referred to as the timer clock (clk t0 ). clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 102 7593a?avr?02/06 at90usb64/128 the double buffered output compare register s (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). see ?output compare unit? on page 103. for details. the compare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 13.1.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a or compar e unit b. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 13-1 are also used extensively throughout the document. 13.2 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0b). for details on clock sources and pres- caler, see ?timer/counter0, timer/counter1, and timer/counter3 prescalers? on page 99 . 13.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 13-2 shows a block diagram of the counter and its surroundings. figure 13-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 103 7593a?avr?02/06 at90usb64/128 clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the c ounter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the sett ing of the wgm01 and wgm00 bits located in the timer/counter control regist er (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are clos e connections between how the counter behaves (counts) and how waveforms are generated on th e output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 106 . the timer/counter overflow flag (tov0) is set a ccording to the mode of operation selected by the wgm02:0 bits. tov0 can be us ed for generating a cpu interrupt. 13.4 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare flag (ocf0a or ocf0 b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is aut omatically cleared when the interrupt is exe- cuted. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the matc h signal to generate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 106 ). figure 13-3 shows a block diagram of the output compare unit. 104 7593a?avr?02/06 at90usb64/128 figure 13-3. output compare unit, block diagram the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the dou- ble buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is dis- abled the cpu will access the ocr0x directly. 13.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc0x) bit. forcin g compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings de fine whether the oc0x pin is set, cleared or toggled). 13.4.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare ma tch that occur in the next timer clock cycle, even when the timer is stopped. this feat ure allows ocr0x to be initial- ized to the same value as tcnt0 without triggeri ng an interrupt when the timer/counter clock is enabled. 13.4.3 using the output compare unit since writing tcnt0 in any mo de of operation will block all compare matches for one timer clock cycle, there are risks involved when ch anging tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 105 7593a?avr?02/06 at90usb64/128 generation. similarly, do not write the tcnt0 value equal to bottom when the counter is down-counting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output com- pare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x1:0 bits are not doubl e buffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 13.5 compare match output unit the compare output mode (com0x1:0) bits have two functions. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits contro l the oc0x pin output source. figure 13-4 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x regist er is reset to ?0?. figure 13-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc0x) from the waveform generator if either of the com0x1:0 bits are se t. however, the oc0x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before th e oc0x value is visi- ble on the pin. the port over ride function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc 0x state before the out- put is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 111. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focn clk i/o 106 7593a?avr?02/06 at90usb64/128 13.5.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tell s the waveform generator that no action on the oc0x register is to be performed on the next co mpare match. for compare output actions in the non-pwm modes refer to table 13-1 on page 112 . for fast pwm mode, refer to table 13-2 on page 112 , and for phase correct pwm refer to table 13-3 on page 112 . a change of the com0x1:0 bits state will have effe ct at the first compare match after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the foc0x strobe bits. 13.6 modes of operation the mode of operation, i.e., t he behavior of the timer/counter an d the output compare pins, is defined by the combination of the waveform ge neration mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 105. ). for detailed timing information see ?timer/counter timing diagrams? on page 110 . 13.6.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maxi mum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in norma l operation the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 13.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 02:0 = 2), the ocr0a register is used to manipulate the counter resolution . in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0 a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 13-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. 107 7593a?avr?02/06 at90usb64/128 figure 13-5. ctc mode, timing diagram an interrupt can be generated each time the c ounter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will mi ss the compare match. the coun ter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, t he oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform ge nerated will have a ma ximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operat ion, the tov0 flag is set in the same timer clock cycle that the counter counts fr om max to 0x00. 13.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the c ounter counts from bottom to top then restarts from bot- tom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the out- put is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast t cntn o cn ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 108 7593a?avr?02/06 at90usb64/128 pwm mode is shown in figure 13-6 . the tcnt0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent com- pare matches between ocr0x and tcnt0. figure 13-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter re aches top. if the inter- rupt is enabled, the interrupt handler routi ne can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com0x1:0 to thr ee: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if th e wgm02 bit is set. this option is not available for the oc0b pin (see table 13-2 on page 112 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pi n is set as output. the pwm waveform is gener- ated by setting (or clearing) the oc0x regi ster at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x regist er at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if t he ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the out put set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag se t 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 109 7593a?avr?02/06 at90usb64/128 feature is similar to the oc0a toggle in ctc mo de, except the double buff er feature of the out- put compare unit is enabled in the fast pwm mode. 13.6.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non- inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while down- counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope pwm modes, t hese modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 13-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slop es represent compare matches between ocr0x and tcnt0. figure 13-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to g enerate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 110 7593a?avr?02/06 at90usb64/128 one allows the oc0a pin to toggle on compare ma tches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 13-3 on page 112 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm wave- form is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, a nd setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrem ents. the pwm fre- quency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mo de. if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the out put will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 13-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. ? ocr0a changes its value from max, like in figure 13-7 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up- counting compare match. ? the timer starts counting from a value higher than the one in ocr0a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 13.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 13-8 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 13-8. timer/counter timing diagram, no prescaling figure 13-9 shows the same timing data, but with the prescaler enabled. f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 111 7593a?avr?02/06 at90usb64/128 figure 13-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 13-10 shows the setting of ocf0b in all mo des and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 13-10. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 13-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 13-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 13.8 8-bit timer/counter register description 13.8.1 timer/counter control register a ? tccr0a tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 com0a 1 com0a 0 com0b 1 com0b 0 ?? wgm0 1 wgm0 0 tccr0a read/write r/w r/w r/w r/w r r r/w r/w 112 7593a?avr?02/06 at90usb64/128 ? bits 7:6 ? com01a:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction r egister (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 13-1 shows the com0a1:0 bit functi onality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 13-2 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 107 for more details. table 13-3 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase cor- rect pwm mode. initial value 0 0 0 0 0 0 0 0 table 13-1. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 13-2. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at top 1 1 set oc0a on compare match, clear oc0a at top table 13-3. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. 113 7593a?avr?02/06 at90usb64/128 note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 109 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction r egister (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 13-1 shows the com0a1:0 bit functi onality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 13-2 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 107 for more details. table 13-3 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase cor- rect pwm mode. table 13-4. compare output mode, non-pwm mode com01 com00 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 13-5. compare output mode, fast pwm mode (1) com01 com00 description 0 0 normal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match, set oc0b at top 1 1 set oc0b on compare match, clear oc0b at top table 13-6. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. 114 7593a?avr?02/06 at90usb64/128 note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 109 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the tccr0b register, these bits control the counting sequence of the counter, the source for maximu m (top) counter value, and what type of wave- form generation to be used, see table 13-7 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 106 ). notes: 1. max = 0xff 2. bottom = 0x00 13.8.2 timer/counter control register b ? tccr0b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the wa veform generation unit . the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. table 13-7. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 10 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 41 0 0reserved ? ? ? 51 0 1 pwm, phase correct ocra top bottom 61 1 0reserved ? ? ? 7 1 1 1 fast pwm ocra top top bit 76543210 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 115 7593a?avr?02/06 at90usb64/128 a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the wa veform generation unit . the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?timer/counter control register a ? tccr0a? on page 111 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the cloc k source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an outpu t. this feature allows software control of the counting. 13.8.3 timer/counter register ? tcnt0 table 13-8. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0 [7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 116 7593a?avr?02/06 at90usb64/128 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying t he counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 13.8.4 output compare register a ? ocr0a the output compare register a contains an 8-bi t value that is conti nuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 13.8.5 output compare register b ? ocr0b the output compare register b contains an 8-bi t value that is conti nuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. 13.8.6 timer/counter interrupt mask register ? timsk0 ? bits 7..3, 0 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabl ed. the corresponding in terrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bi t is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and th e i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and t he i-bit in the status register is set, the timer/counter0 overflow interr upt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occu rs, i.e., when the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. bit 76543210 ocr0a [7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0b [7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 10 ????? ocie0bocie0atoie0timsk0 read/writerrrrr r/wr/wr/w initial value00000 0 00 117 7593a?avr?02/06 at90usb64/128 13.8.7 timer/counter 0 interrupt flag register ? tifr0 ? bits 7..3, 0 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the cor- responding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (tim er/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occu rs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the cor- responding interrupt handling vector. alternativel y, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (tim er/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 co mpare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i- bit, toie0 (timer/counter 0 overflow interrupt enable), and tov0 are set, the timer/co unter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 13-7 , ?waveform generation mode bit description? on page 114 . bit 76543210 ?????ocf0bocf0a tov0 tifr0 read/writerrrrrr/wr/wr/w initial value00000000 118 7593a?avr?02/06 at90usb64/128 14. 16-bit timer/counter (timer /counter1 and timer/counter3) the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. the main features are: ? true 16-bit design (i.e., allows 16-bit pwm) ? three independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? twenty independent inte rrupt sources (tov1, ocf1a, ocf1b, ocf1c, icf1, tov3, ocf3a, ocf3b, ocf3c, icf3, tov4, ocf4a, ocf4b, oc f4c, icf4, tov5, ocf5a, ocf5b, ocf5c and icf5) 14.1 overview most register and bit references in this sect ion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 14-1 . for the actual placement of i/o pins, see ?pinout at90usb64/128-tqfp? on page 3 . cpu accessible i/o reg- isters, including i/o bits and i/o pins, are shown in bold. the devi ce-specific i/o register and bit locations are listed in the ?16-bit timer/counter (timer/count er1 and timer/counter3)? on page 118 . the power reduction timer/counter1 bit, prtim1, in ?power reduction register 0 - prr0? on page 55 must be written to zero to enable timer/counter1 module. the power reduction timer/counter3 bit, prtim3, in ?power reduction register 1 - prr1? on page 56 must be written to zero to enable timer/counter3 module. 119 7593a?avr?02/06 at90usb64/128 figure 14-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-1 on page 3 , table 10-6 on page 81 , and table 10-9 on page 84 for timer/counter1 and 3 and 3 pin placement and description. 14.1.1 registers the timer/counter (tcntn), output compare registers (ocrna/b/c), and input capture reg- ister (icrn) are all 16-bit regi sters. special procedures must be followed when accessing the 16- bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 120 . the timer/counter control registers (tccrna/b/c) are 8-bit registers and have no cpu access restrictions. interrupt requests (short en as int.req.) signals are all visible in the timer interrupt flag register (t ifrn). all interrupts are individually masked with the timer inter- rupt mask register (timskn). tifrn and timskn are not shown in the figure since these registers are shared by other timer units. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block contro ls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare regi sters (ocrna/b/c) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform gener- ator to generate a pwm or variable frequency output on the output compare pin (ocna/b/c). icfn (int.req.) tovn (int.req.) clock select timer/counter databus icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector ( from prescaler ) tclk ocrnc ocrnb ocrna 120 7593a?avr?02/06 at90usb64/128 see ?output compare units? on page 127. . the compare match event will also set the compare match flag (ocfna/b/c) which can be used to generate an output compare interrupt request. the input capture register can c apture the timer/counter value at a given external (edge trig- gered) event on either the input capture pin (icpn) or on the analog comparator pins ( see ?analog comparator? on page 313. ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter valu e, can in some modes of operation be defined by either the ocrna register, the icrn regist er, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna register can not be used for generating a pwm output. however, the top value will in this case be do uble buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 14.1.2 definitions the following definitions are used ex tensively throughout the document: 14.2 accessing 16-bit registers the tcntn, ocrna/b/c, and icrn are 16-bit r egisters that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write opera- tions. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16- bit access. the same temporary register is shared between all 16-bit registers within each 16- bit timer. accessing the low byte tr iggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the hi gh byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same cl ock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same cloc k cycle as the low byte is read. not all 16-bit accesses uses the temporary regi ster for the high byte . reading the ocrna/b/c 16-bit registers does not involv e using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrna/b/c and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be a ssigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocrna or icrn register. the assignment is depende nt of the mode of operation. 121 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. the assembly code example returns the t cntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the a ccess outside the interrupt will be co rrupted. therefor e, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcntn register contents. reading any of the ocrna/b/c or icrn registers can be done by using the same principle. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... assembly code example (1) 122 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. the assembly code example returns the t cntn value in the r17:r16 register pair. the following code examples show how to do an at omic write of the tcntn register contents. writing any of the ocrna/b/c or icrn registers can be done by using the same principle. tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } assembly code example (1) 123 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. the assembly code example requires that the r17: r16 register pair contains the value to be writ- ten to tcntn. 14.2.1 reusing the temporary high byte register if writing to more than one 16-bit register where th e high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 14.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see ?timer/counter0, timer/counter1, and timer/counter3 prescalers? on page 99 . 14.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 14-2 shows a block diagram of the counter and its surroundings. tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 124 7593a?avr?02/06 at90usb64/128 figure 14-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcntnh) con- taining the upper eight bits of the counter, and counter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirectly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register va lue when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcntn register when the counter is counting that will gi ve unpredictable results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the co unter is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock sour ce is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, independent of whether clk t n is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs ocnx. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 130 . the timer/counter overflow flag (tovn) is set a ccording to the mode of operation selected by the wgmn3:0 bits. tovn can be us ed for generating a cpu interrupt. temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 125 7593a?avr?02/06 at90usb64/128 14.5 input capture unit the timer/counter incorporates an input capture un it that can capture exte rnal events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icpn pin or al ternatively, for the timer/counter1 only, via the analog comparator unit. the time-stamps can th en be used to calculate frequency, duty-cycle, and other features of the signal applied. altern atively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 14-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 14-3. input capture unit block diagram note: the analog comparator output (aco) ca n only trigger the timer/counter1 icp ? not timer/counter3, 4 or 5. when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a captur e is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is c opied into icrn register. if enabled (ticien = 1), the input capture flag generate s an input capture interrupt. the icfn flag is automatically cleared when the interrupt is executed. alternativ ely the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). when the low byte is read the high byte is copied into the high byte temporary register (temp). when the cpu reads the icrnh i/o location it will access the temp register. icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* 126 7593a?avr?02/06 at90usb64/128 the icrn register can only be written when using a waveform g eneration mode that utilizes the icrn register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgmn3:0) bits must be set before t he top value can be written to the icrn register. when writing the icrn regi ster the high byte must be wr itten to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 120 . 14.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the analog comparator output (aco) inputs are sampled using the same technique as for the tn pin ( figure 1 on page 99 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases t he delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabl ed unless the timer/counter is set in a wave- form generation mode that uses icrn to define top. an input capture can be tri ggered by software by controllin g the port of the icpn pin. 14.5.2 noise canceler the noise canceler improves noise immunity by using a simple digita l filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 14.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured valu e in the icrn register before the next event occurs, the icrn will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture in terrupt, the icrn register shoul d be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn 127 7593a?avr?02/06 at90usb64/128 register has been read. after a change of the e dge, the input capture fl ag (icfn) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not re quired (if an interrupt handler is used). 14.6 output compare units the 16-bit comparator continuously compares tcntn with the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next timer clock cycle. if enabled (ocienx = 1), the output com- pare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is executed. alternatively the ocfnx flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 130. ) a special feature of output comp are unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter re solution, the top value defines the period time for waveforms generated by the waveform generator. figure 14-4 shows a block diagram of the output compar e unit. the small ?n? in the register and bit names indicates the device number (n = n for timer/counter n), and the ?x? indicates output compare unit (a/b/c). the elements of the block diagram that are not dire ctly a part of the out- put compare unit are gray shaded. figure 14-4. output compare unit, block diagram the ocrnx register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buff ering synchronizes the update of the ocrnx com- pare register to either top or bottom of the counting sequence. the synchronization ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 128 7593a?avr?02/06 at90usb64/128 prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out- put glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is dis- abled the cpu will access the ocrnx directly. t he content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not r ead via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the oc rnx registers must be done via the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare register in the same system clock cycle. for more information of how to acce ss the 16-bit registers refer to ?accessing 16-bit registers? on page 120 . 14.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forcing compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real compare match had occurred (the comn1:0 bits settings define whether the ocnx pin is set, cleared or toggled). 14.6.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that o ccurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tcntn without triggering an inte rrupt when the timer/counter clock is enabled. 14.6.3 using the output compare unit since writing tcntn in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changi ng tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the compare matc h will be missed, resulting in incorrect wave- form generation. do not write the tcntn equal to top in pwm modes with variable top values. the compare match for the top will be ig nored and the counter will continue to 0xffff. similarly, do not write the tcntn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output com- pare (focnx) strobe bits in normal mode. the ocnx register keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not doubl e buffered together with the compare value. changing the comnx1:0 bits will take effect immediately. 14.7 compare match output unit the compare output mode (comnx1:0) bits have two functions. the waveform generator uses the comnx1:0 bits for defining the output com pare (ocnx) state at the next compare match. 129 7593a?avr?02/06 at90usb64/128 secondly the comnx1:0 bits control the ocnx pin output source. figure 14-5 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are shown. when referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system reset occur, the ocnx regist er is reset to ?0?. figure 14-5. compare match output unit, schematic the general i/o port function is overridden by the output compare (ocnx) from the waveform generator if either of the comnx1:0 bits are se t. however, the ocnx pin direction (input or out- put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be set as output before th e ocnx value is visi- ble on the pin. the port override function is generally independ ent of the waveform generation mode, but there are some exceptions. refer to table 14-1 , table 14-2 and table 14-3 for details. the design of the output compare pin logic allows initialization of the oc nx state before the out- put is enabled. note that some comnx1:0 bit settings are reserved for certain modes of operation. see ?16-bit timer/counter (timer/counter1 and timer/counter3)? on page 118. the comnx1:0 bits have no effect on the input capture unit. 14.7.1 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tell s the waveform generator that no action on the ocnx register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 14-1 on page 141 . for fast pwm mode refer to table 14-2 on page 141 , and for phase correct and phase and frequency correct pwm refer to table 14-3 on page 142 . port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 130 7593a?avr?02/06 at90usb64/128 a change of the comnx1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the focnx strobe bits. 14.8 modes of operation the mode of operation, i.e., t he behavior of the timer/counter an d the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the comnx1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 128. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 137 . 14.8.1 normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit valu e (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn become s zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag , the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generat e interrupts at some given time. using the output compare to gene rate waveforms in norm al mode is not recommended, since this will occupy too much of the cpu time. 14.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches either the oc rna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value fo r the counter, hence also its resolution. this mode allows greater control of the compare match ou tput frequency. it also simplifies the opera- tion of counting external events. the timing diagram for the ctc mode is shown in figure 14-6 . the counter value (tcntn) increases until a compare match occurs with eith er ocrna or icrn, and then counter (tcntn) is cleared. 131 7593a?avr?02/06 at90usb64/128 figure 14-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routi ne can be used for updating the top value. how- ever, changing the top to a value close to bo ttom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buff- ering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the co mpare match. the counter will then have to count to its max- imum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is no t desirable. an alternative will then be to use the fast pwm mode using ocrna for defining top (w gmn3:0 = 15) since the ocrna then will be doub le buffered. for generating a waveform output in ctc mode, t he ocna output can be set to toggle its logical level on each compare match by setting the co mpare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). th e waveform generated will have a maximum fre- quency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0 x0000). the wavefo rm frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operat ion, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 14.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compare match between tcntn and ocrnx, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mo de can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre- quency makes the fast pwm mode well suited fo r power regulation, re ctification, and dac applications. high frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = 132 7593a?avr?02/06 at90usb64/128 the pwm resolution for fast pwm can be fixed to 8- , 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the max- imum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the co unter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). th e counter is then cleared at the following timer clock cycle. the timing diagram fo r the fast pwm mode is shown in figure 14-7 . the figure shows fast pwm mode when ocrna or icrn is us ed to define top. the tcntn value is in the timing diagram shown as a histogram for illu strating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 14-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set eac h time the counter reac hes top. in addition the ocna or icfn flag is set at the same time r clock cycle as tovn is set when either ocrna or icrn is used for defining the top value. if o ne of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will nev er occur between the tcntn and the ocrnx. note that when using fixed top values the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna when used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a lo w prescaler value, there is a risk that the new icrn value written is lower than the current value of tcntn. the result will then be that the counter will miss the compare matc h at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx / top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 133 7593a?avr?02/06 at90usb64/128 to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. th e ocrna compare register will th en be updated with the value in the buffer register at the next timer clo ck cycle the tcntn matches to p. the update is done at the same timer clock cycle as the tcnt n is cleared and the tovn flag is set. using the icrn register for defining top work s well when using fixed top values. by using icrn, the ocrna register is free to be used fo r generating a pwm output on ocna. however, if the base pwm frequency is actively change d (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 141 ). the actual ocnx value will only be visible on the port pin if th e data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register re presents special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the out- put will be a narrow spike for eac h top+1 timer clock cycle. se tting the ocrnx equal to top will result in a const ant high or low output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting ocna to toggle its logical level on each co mpare match (comna1:0 = 1). this applies only if ocr1a is used to define the top value (wgm 13:0 = 15). the wave form generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output com- pare unit is enabled in the fast pwm mode. 14.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric featur e of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = 134 7593a?avr?02/06 at90usb64/128 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu- tion in bits can be calculated by using the following equation: in phase correct pwm mode the counter is increm ented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x 03ff (wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direct ion. the tcntn value will be equa l to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 14-8 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrati ng the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx inter- rupt flag will be set when a compare match occurs. figure 14-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is se t each time the counter reaches bottom. when either ocrna or icrn is used for defining the top value, the ocna or icfn flag is set accord- ingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interrupt fl ags can be used to generate an in terrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will nev er occur between the tcntn and the ocrnx. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 14-8 illustrates, changing the top actively while the timer/counter is runni ng in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx reg- r pcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 135 7593a?avr?02/06 at90usb64/128 ister. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by th e new top value. when thes e two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differ ences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by sett ing the comnx1:0 to three (see table 14-3 on page 142 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by se tting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pw m frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register re present special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13 :0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 14.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high reso lution phase and frequency correct pwm wave- form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. howe ver, due to the symme tric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is up dated by the ocrnx buffer register, (see figure 14- 8 and figure 14-9 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = 136 7593a?avr?02/06 at90usb64/128 the maximum resolution is 16-bit (icrn or ocrn a set to max). the pwm re solution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reach ed the top and changes t he count direction. t he tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 14-9 . the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to defi ne top. the tcntn value is in the timing dia- gram shown as a histogram for illustrating the dual-slope operati on. the diagram includes non- inverted and inverted pwm outputs. the small hor izontal line marks on t he tcntn slopes repre- sent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 14-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set at the same timer cloc k cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcntn and the ocrnx. as figure 14-9 shows the output generated is, in contra st to the phase correct mode, symmetri- cal in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. r pfcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag se t (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 137 7593a?avr?02/06 at90usb64/128 using the icrn register for defining top work s well when using fixed top values. by using icrn, the ocrna register is free to be used fo r generating a pwm output on ocna. however, if the base pwm frequency is actively changed by changing the top value, using the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm wave- forms on the ocnx pins. settin g the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table 14-3 on page 142 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter incre- ments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrem ents. the pwm frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register re presents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non- inverted pwm mode. for in verted pwm the output will have the opposite lo gic values. if ocr1a is used to define the top va lue (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 14.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocrnx register is updated with the ocrnx buffer value (only for modes utilizing double buffering). figure 14-10 shows a timing diagram fo r the setting of ocfnx. figure 14-10. timer/counter timing diagram, setting of ocfnx, no prescaling figure 14-11 shows the same timing data, but with the prescaler enabled. f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = clk tn (clk i/o /1) o cfnx clk i/o o crnx t cntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 138 7593a?avr?02/06 at90usb64/128 figure 14-11. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 14-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. figure 14-12. timer/counter timing diagram, no prescaling figure 14-13 shows the same timing data, but with the prescaler enabled. o cfnx o crnx t cntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn ( pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o 139 7593a?avr?02/06 at90usb64/128 figure 14-13. timer/counter timing diagram, with prescaler (f clk_i/o /8) 14.10 16-bit timer/counte r register description 14.10.1 timer/counter1 control register a ? tccr1a 14.10.2 timer/counter3 control register a ? tccr3a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b ? bit 3:2 ? comnc1:0: compare output mode for channel c the comna1:0, comnb1:0, and comnc1:0 control the output compare pins (ocna, ocnb, and ocnc respectively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bits are written to one, the ocnb output overrides the normal port func- tionality of the i/o pin it is connected to. if one or both of the comnc1:0 bi ts are written to one, the ocnc output overrides the normal port functi onality of the i/o pin it is connected to. how- ever, note that the data direction register (ddr) bit corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output driver. tovn (fpwm) a nd icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 com1a 1 com1a 0 com1b 1 com1b 0 com1c 1 com1c 0 wgm11 wgm1 0 tccr1 a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 com3a 1 com3a 0 com3b 1 com3b 0 com3c 1 com3c 0 wgm3 1 wgm3 0 tccr3 a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 140 7593a?avr?02/06 at90usb64/128 when the ocna, ocnb or ocnc is connected to t he pin, the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 14-1 shows the comnx1:0 bi t functionality when the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). 141 7593a?avr?02/06 at90usb64/128 . table 14-2 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to the fast pwm mode. note: a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 107. for more details. table 14-3 shows the comnx1:0 bit functionality wh en the wgmn3:0 bits are set to the phase correct and frequency correct pwm mode. table 14-1. compare output mode, non-pwm comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 toggle ocna/ocnb/ocnc on compare match. 10 clear ocna/ocnb/ocnc on compare match (set output to low level). 11 set ocna/ocnb/ocnc on compare match (set output to high level). table 14-2. compare output mode, fast pwm comna1/comnb1/ comnc0 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgm13:0 = 14 or 15: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 10 clear ocna/ocnb/ocnc on compare match, set ocna/ocnb/ocnc at top 11 set ocna/ocnb/ocnc on compare match, clear ocna/ocnb/ocnc at top 142 7593a?avr?02/06 at90usb64/128 note: a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1//comnc1 is set. see ?phase correct pwm mode? on page 109. for more details. ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tc crnb register, these bits control the counting sequence of the counter, the source for maximu m (top) counter value, and what type of wave- form generation to be used, see table 14-4 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?modes of operation? on page 106. ). table 14-3. compare output mode, phase correct and phase and frequency correct pwm comna1/comnb/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgm13:0 = 8, 9 10 or 11: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 10 clear ocna/ocnb/ocnc on compare match when up-counting. set ocna/ocnb/ocnc on compare match when downcounting. 11 set ocna/ocnb/ocnc on compare match when up-counting. clear ocna/ocnb/ocnc on compare match when downcounting. 143 7593a?avr?02/06 at90usb64/128 note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 14.10.3 timer/counter1 control register b ? tccr1b 14.10.4 timer/counter3 control register b ? tccr3b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the input capture pin (icp n) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select table 14-4. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icrn bottom bottom 91001 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn top top 15 1 1 1 1 fast pwm ocrna top top bit 76543210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/write r/w r/w r r/w r/w r/w r/w r/w initial value00000000 144 7593a?avr?02/06 at90usb64/128 this bit selects which edge on the input capture pin (icpn) that is used to trigger a capture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will al so set the input capture flag (icfn), and this can be used to cause an input capture in terrupt, if this in terrupt is enabled. when the icrn is used as top value (see descr iption of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future devi ces, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. ? bit 2:0 ? csn2:0: clock select the three clock select bits se lect the clock source to be us ed by the timer/counter, see figure 13-8 and figure 13-9 . 145 7593a?avr?02/06 at90usb64/128 if external pin modes are used for the timer/countern, transitions on the tn pin will clock the counter even if the pin is configured as an outpu t. this feature allows software control of the counting. 14.10.5 timer/counter1 control register c ? tccr1c 14.10.6 timer/counter3 control register c ? tccr3c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b ? bit 5 ? focnc: force output compare for channel c the focna/focnb/focnc bits are only active when the wgmn3:0 bits specifies a non-pwm mode. when writing a logical one to the fo cna/focnb/focnc bit, an immediate compare match is forced on the waveform generation un it. the ocna/ocnb/ocnc output is changed according to its comnx1:0 bits setting. note that the focna/focnb/focnc bits are imple- mented as strobes. therefore it is the value pr esent in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb/focnc strobe will no t generate any interr upt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb/focnb bits are always read as zero. ? bit 4:0 ? reserved bits these bits are reserved for future use. for ensuring compatibility with future devices, these bits must be written to zero when tccrnc is written. 14.10.7 timer/counter1 ? tcnt1h and tcnt1l table 14-5. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source. (timer/counter stopped) 001clk i/o /1 (no prescaling 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge 1 1 1 external clock source on tn pin. clock on rising edge bit 7654 3 210 foc1a foc1b foc1c ? ? ? ? ? tccr1c read/write w w w r r r r r initial value 0 0 0 0 0 0 0 0 bit 7654 3 210 foc3a foc3b foc3c ? ? ? ? ? tccr3c read/write w w w r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 146 7593a?avr?02/06 at90usb64/128 14.10.8 timer/counter3 ? tcnt3h and tcnt3l the two timer/counter i/o locations (tcntnh and tcntnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporar y high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 120. modifying the counter (tcntn) while the counte r is running introduces a risk of missing a com- pare match between tcntn and one of the ocrnx registers. writing to the tcntn register blocks (removes ) the compare match on the following timer clock for all compare units. 14.10.9 output compare regist er 1 a ? ocr1ah and ocr1al 14.10.10 output compare regi ster 1 b ? ocr1bh and ocr1bl 14.10.11 output compare regi ster 1 c ? ocr1ch and ocr1cl 14.10.12 output compare regi ster 3 a ? ocr3ah and ocr3al tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 tcnt3[15:8] tcnt3h tcnt3[7:0] tcnt3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1c[15:8] ocr1ch ocr1c[7:0] ocr1cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3a[15:8] ocr3ah ocr3a[7:0] ocr3al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 147 7593a?avr?02/06 at90usb64/128 14.10.13 output compare regi ster 3 b ? ocr3bh and ocr3bl 14.10.14 output compare regi ster 3 c ? ocr3ch and ocr3cl the output compare registers contain a 16-bit value that is continuo usly compared with the counter value (tcntn). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to thes e registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 120. 14.10.15 input capture register 1 ? icr1h and icr1l 14.10.16 input capture register 3 ? icr3h and icr3l the input capture is updated with the counter (tcntn) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 120. 14.10.17 timer/counter1 interr upt mask register ? timsk1 bit 76543210 ocr3b[15:8] ocr3bh ocr3b[7:0] ocr3bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr3c[15:8] ocr3ch ocr3c[7:0] ocr3cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 icr3[15:8] icr3h icr3[7:0] icr3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ?icie1 ?ocie1 c ocie1b ocie1a toie1 timsk1 read/write r r r/w r r/w r/w r/w r/w initial value00000000 148 7593a?avr?02/06 at90usb64/128 14.10.18 timer/counter3 interr upt mask register ? timsk3 ? bit 5 ? icien: timer/countern, input capture interrupt enable when this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 69. ) is executed when the icfn fl ag, located in tifrn, is set. ? bit 3 ? ocienc: timer/countern, output compare c match interrupt enable when this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 69. ) is executed when the ocfnc flag, located in tifrn, is set. ? bit 2 ? ocienb: timer/countern, output compare b match interrupt enable when this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 69. ) is executed when the ocfnb flag, located in tifrn, is set. ? bit 1 ? ociena: timer/countern, output compare a match interrupt enable when this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 69. ) is executed when the ocfna flag, located in tifrn, is set. ? bit 0 ? toien: timer/counte rn, overflow interrupt enable when this bit is written to one, and the i-flag in t he status register is set (interrupts globally enabled), the timer/countern overflow interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 69. ) is executed when the tovn fl ag, located in tifrn, is set. 14.10.19 timer/counter1 interr upt flag register ? tifr1 14.10.20 timer/counter3 interr upt flag register ? tifr3 ? bit 5 ? icfn: timer/countern, input capture flag bit 76543210 ? ?icie3 ?ocie3 c ocie3b ocie3a toie3 timsk3 read/write r r r/w r r/w r/w r/w r/w initial value00000000 bit 76543210 ? ?icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/writer r r/wr r/wr/wr/wr/w initial value00000000 bit 76543210 ? ?icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/writer r r/wr r/wr/wr/wr/w initial value00000000 149 7593a?avr?02/06 at90usb64/128 this flag is set when a capture event occurs on the icpn pin. when the input capture register (icrn) is set by the wgmn3:0 to be used as the top value, the icfn flag is set when the counter reaches the top value. icfn is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icfn can be cleared by writing a logic one to its bit location. ? bit 3? ocfnc: timer/countern, output compare c match flag this flag is set in the timer clock cycle after the counter (t cntn) value matches the output compare register c (ocrnc). note that a forced output compare (foc nc) strobe will not set the ocfnc flag. ocfnc is automatically cleared when the outp ut compare match c interrupt vector is exe- cuted. alternatively, ocfnc can be cleared by writing a logic one to its bit location. ? bit 2 ? ocfnb: timer/counter1, output compare b match flag this flag is set in the timer clock cycle after the counter (t cntn) value matches the output compare register b (ocrnb). note that a forced output compare (foc nb) strobe will not set the ocfnb flag. ocfnb is automatically cleare d when the output compare matc h b interrupt vector is exe- cuted. alternatively, ocfnb can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the counter (tcntn value matches the output com- pare register a (ocrna). note that a forced output compare (foc na) strobe will not set the ocfna flag. ocfna is automatically cleare d when the output compare matc h a interrupt vector is exe- cuted. alternatively, ocfna can be cleared by writing a logic one to its bit location. ? bit 0 ? tovn: timer/countern, overflow flag the setting of this flag is dependent of the wg mn3:0 bits setting. in normal and ctc modes, the tovn flag is set when the timer overflows. refer to table 14-4 on page 143 for the tovn flag behavior when using another wgmn3:0 bit setting. tovn is automatically cleared wh en the timer/countern overflow interrupt vector is executed. alternatively, tovn can be cleared by writing a logic one to its bit location. 150 7593a?avr?02/06 at90usb64/128 15. 8-bit timer/counter2 with pwm and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare ma tch interrupt sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32 khz watch crystal independent of the i/o clock 15.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 15-1.. for the actual placement of i/o pins, see ?pin configurations? on page 3 . cpu accessible i/o registers, includ- ing i/o bits and i/o pins, are shown in bold. t he device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 161 . the power reduction timer/counter2 bit, prtim2, in ?power reduction register 0 - prr0? on page 55 must be written to zero to enable timer/counter2 module. figure 15-1. 8-bit timer/counter block diagram timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb clk tn assrn synchronization unit prescaler t/c oscillator clk i/o clk asy asynchronous mode select (asn) synchronized status flags tosc1 tosc2 status flags clk i/o 151 7593a?avr?02/06 at90usb64/128 15.1.1 registers the timer/counter (tcnt2) and output compare register (ocr2a and ocr2b) are 8-bit reg- isters. interrupt request (abbreviate d to int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this sect ion. the asynchronous operation is controlled by the asynchronous status regist er (assr). the clock select lo gic block controls which clock source the timer/counter uses to increment (or de crement) its value. the timer/counter is inac- tive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 152. for details. the compare match event will also set the compare flag (ocf2a or ocf2b) which can be used to generate an output compare interrupt request. 15.1.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for ac cessing timer/counter2 counter value and so on. the definitions in table 15-1 are also used extensively throughout the section. 15.2 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connecte d to tosc1 and tosc2. for details on asynchronous operation, see ?asyn- chronous status register ? assr? on page 166 . for details on clock so urces and prescaler, see ?timer/counter prescaler? on page 170 . 15.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 15-2 shows a block diagram of the coun ter and its surrounding environment. bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. 152 7593a?avr?02/06 at90usb64/128 figure 15-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the co unter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). w hen no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the sett ing of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in the timer/counter control register b (tccr2b). there are clos e connections between how the counter behaves (counts) and how waveforms are generated on th e output compare outputs oc2a and oc2b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 155 . the timer/counter overflow flag (tov2) is set a ccording to the mode of operation selected by the wgm22:0 bits. tov2 can be us ed for generating a cpu interrupt. 15.4 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or ocr2b, the comparator signals a match. a match will set the output compare flag (ocf2a or ocf2b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is aut omatically cleared when the interrupt is exe- cuted. alternatively, the output compare flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generato r uses the match signal to generate an output according to operating mode set by the wgm22: 0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the waveform ge nerator for hand ling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 155 ). figure 14-10 on page 137 shows a block diagram of the output compare unit. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 153 7593a?avr?02/06 at90usb64/128 figure 15-3. output compare unit, block diagram the ocr2x register is double buffered when usi ng any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is dis- abled the cpu will access the ocr2x directly. 15.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc2x) bit. forci ng compare match will not set the ocf2x flag or reload/clear the timer, but the oc2x pin will be updated as if a real compare match had occurred (the com2x1:0 bits settings de fine whether the oc2x pin is set, cleared or toggled). 15.4.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any com pare match that occurs in the next timer clock cycle, even when the timer is stopped. this feat ure allows ocr2x to be initial- ized to the same value as tcnt2 without triggeri ng an interrupt when the timer/counter clock is enabled. 15.4.3 using the output compare unit since writing tcnt2 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the time r/counter is running or not. if the value written to tcnt2 equals the ocr2x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 154 7593a?avr?02/06 at90usb64/128 the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output com- pare (foc2x) strobe bit in normal mode. the oc2x register keeps its value even when changing between waveform generation modes. be aware that the com2x1:0 bits are not doubl e buffered together with the compare value. changing the com2x1:0 bits will take effect immediately. 15.5 compare match output unit the compare output mode (com2x1:0) bits have two functions. the waveform generator uses the com2x1:0 bits for defining the output com pare (oc2x) state at the next compare match. also, the com2x1:0 bits contro l the oc2x pin output source. figure 15-4 shows a simplified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are shown. when referring to the oc2x state, the reference is for the internal oc2x register, not the oc2x pin. figure 15-4. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc2x) from the waveform generator if either of the com2x1:0 bits are se t. however, the oc2x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc2x pin (ddr_oc2x) must be set as output before th e oc2x value is visi- ble on the pin. the port over ride function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc 2x state before the out- put is enabled. note that some com2x1:0 bit settings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on page 161. port ddr dq dq ocn x pin ocnx dq waveform generator c omnx1 c omnx0 0 1 data b u s f ocnx clk i/o 155 7593a?avr?02/06 at90usb64/128 15.5.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tell s the waveform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 15-4 on page 162 . for fast pwm mode, refer to table 15-5 on page 163 , and for phase correct pwm refer to table 15-6 on page 163 . a change of the com2x1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-pwm modes, the action can be fo rced to have immediate effect by using the foc2x strobe bits. 15.6 modes of operation the mode of operation, i.e., t he behavior of the timer/counter an d the output compare pins, is defined by the combination of the waveform ge neration mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2x1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com2x1:0 bits control whethe r the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 154. ). for detailed timing information refer to ?timer/counter timing diagrams? on page 159 . 15.6.1 normal mode the simplest mode of operation is the normal mode (wgm22:0 = 0). in this mode the counting direction is always up (incre menting), and no counter clear is performed. the counter simply overruns when it passes its maxi mum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in norma l operation the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 15.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 22:0 = 2), the ocr2a register is used to manipulate the counter resolution . in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2 a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in table 15-5 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2 a, and then counter (tcnt2) is cleared. 156 7593a?avr?02/06 at90usb64/128 figure 15-5. ctc mode, timing diagram an interrupt can be generated each time the c ounter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compar e match. the counter will t hen have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, t he oc2a output can be set to toggle its logical level on each compare match by setting the co mpare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the wavefo rm generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts fr om max to 0x00. 15.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the c ounter counts from bottom to top then restarts from bot- tom. top is defined as 0xff when wgm22:0 = 3, and ocr2a when mgm22:0 = 7. in non- inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x, and set at bottom. in inverting compare output mode, the out- put is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. t cntn o cnx ( toggle) ocnx interrupt flag set 1 4 p eriod 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 157 7593a?avr?02/06 at90usb64/128 in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 15-6 . the tcnt2 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. figure 15-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter re aches top. if the inter- rupt is enabled, the interrupt handler routi ne can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com2x1:0 to thre e. top is defined as 0xff when wgm2:0 = 3, and ocr2a when wgm2:0 = 7 (see table 15-2 on page 162 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm wave- form is generated by setting (or clearing) the oc2x register at the compare match between ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if t he ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the out put set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform out put in fast pwm mode can be achieved by set- ting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the waveform tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 158 7593a?avr?02/06 at90usb64/128 generated will have a ma ximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this fea- ture is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 15.6.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm22:0 = 1, and ocr2a when mgm22:0 = 5. in non- inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x while upcounting, and set on the compare match while downcount- ing. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmet- ric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt2 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 15-7 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 sl opes represent compare matches between ocr2x and tcnt2. figure 15-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to g enerate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two w ill produce a non-inverted pwm. an inverted pwm tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 159 7593a?avr?02/06 at90usb64/128 output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 15-3 on page 162 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or sett ing) the oc2x register at the compare match between ocr2x and tcnt2 when the counter increments, and setting (or clearing) the oc2x register at compare match between ocr2x and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the follow- ing equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mo de. if the ocr2a is set equal to bottom, the output will be continuously low and if set equal to max the out put will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 15-7 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. ? ocr2a changes its value from max, like in figure 15-7 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up- counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 15.7 timer/counter timing diagrams the following figures show t he timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 15-8 contains timing data for basic timer/counter operati on. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 15-8. timer/counter timing diagram, no prescaling f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o t cntn max - 1 max bottom bottom + 1 160 7593a?avr?02/06 at90usb64/128 figure 15-9 shows the same timing data, but with the prescaler enabled. figure 15-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 15-10 shows the setting of ocf2a in all modes except ctc mode. figure 15-10. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) figure 15-11 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. tovn t cntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx t cntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 161 7593a?avr?02/06 at90usb64/128 figure 15-11. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) 15.8 8-bit timer/counter register description 15.8.1 timer/counter control register a ? tccr2a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction re gister (ddr) bit corresponding to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 15-1 shows the com2a1:0 bit functi onality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). ocfnx ocrnx t cntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 com2a 1 com2a 0 com2b 1 com2b 0 ?? wgm2 1 wgm2 0 tccr2a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-1. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match 162 7593a?avr?02/06 at90usb64/128 table 15-2 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 156 for more details. table 15-3 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 158 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) behavior. if one or both of the com2b1:0 bits are set, the oc2b output overrides the normal po rt functionality of the i/o pin it is connected to. however, note that the data direction re gister (ddr) bit corresponding to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 15-4 shows the com2b1:0 bit functi onality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 15-2. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port oper ation, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match, set oc2a at top 1 1 set oc2a on compare match, clear oc2a at top table 15-3. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port oper ation, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. table 15-4. compare output mode, non-pwm mode com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match 163 7593a?avr?02/06 at90usb64/128 table 15-5 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the se t or clear is done at top. see ?fast pwm mode? on page 156 for more details. table 15-6 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 158 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the wgm22 bit found in the tccr2b register, these bits control the counting sequence of the counter, the source for maximu m (top) counter value, and what type of wave- form generation to be used, see table 15-7 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 155 ). table 15-5. compare output mode, fast pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 1 0 clear oc2b on compare match, set oc2b at top 1 1 set oc2b on compare match, clear oc2b at top table 15-6. compare output mode, phase correct pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 11 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. table 15-7. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 10 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 164 7593a?avr?02/06 at90usb64/128 notes: 1. max= 0xff 2. bottom= 0x00 15.8.2 timer/counter control register b ? tccr2b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2a bit, an immediate compare match is forced on the wa veform generation unit . the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2b bit, an immediate compare match is forced on the wa veform generation unit . the oc2b output is changed according to its com2b1:0 bits setting. note that the foc2b bit is implemented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. 3 0 1 1 fast pwm 0xff top max 41 0 0reserved ? ? ? 51 0 1 pwm, phase correct ocra top bottom 61 1 0reserved ? ? ? 7 1 1 1 fast pwm ocra top top table 15-7. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) bit 76543210 foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 165 7593a?avr?02/06 at90usb64/128 ? bit 3 ? wgm22: waveform generation mode see the description in the ?timer/counter control register a ? tccr2a? on page 161 . ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 15-8 . if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an outpu t. this feature allows software control of the counting. 15.8.3 timer/counter register ? tcnt2 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying t he counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. 15.8.4 output compare register a ? ocr2a the output compare register a contains an 8-bi t value that is conti nuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. 15.8.5 output compare register b ? ocr2b table 15-8. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 tcnt2 [7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr2a [7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr2b [7:0] ocr2b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 166 7593a?avr?02/06 at90usb64/128 the output compare register b contains an 8-bi t value that is conti nuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. 15.9 asynchronous operation of the timer/counter 15.9.1 asynchronous status register ? assr ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the crystal oscilla tor will only run when this bit is zero. ? bit 5 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/counte r2 is clocked from the i/o clock, clk i/o . when as2 is written to one, timer/counter2 is clocked from a crystal oscilla tor connected to the timer oscil- lator 1 (tosc1) pin. when the value of as2 is changed, the contents of tcnt2, ocr2a, ocr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 3 ? ocr2aub: output compare register2 update busy when timer/counter2 operates asynchronously and oc r2a is written, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and oc r2b is written, this bit becomes set. when ocr2b has been updated from the temporary storage register, this bit is cleared by hard- ware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates as ynchronously and tccr2a is writ ten, this bit becomes set. when tccr2a has been updated fr om the temporary storage regi ster, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub: timer/counter control register2 update busy when timer/counter2 operates as ynchronously and tccr2b is writ ten, this bit becomes set. when tccr2b has been updated fr om the temporary storage regi ster, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is ready to be updated with a new value. bit 7 6 5 4 3 2 1 0 ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 167 7593a?avr?02/06 at90usb64/128 if a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, ocr2b, tccr2a and tccr2b are different. when reading tcnt2, the actual timer value is read. when reading oc r2a, ocr2b, tccr2a and tccr2b the value in the temporary storage register is read. 15.9.2 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when switching between asynch ronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2x and toie2. b. select clock source by setting as2 as appropriate. c. write new values to t cnt2, ocr2x, and tccr2x. d. to switch to asynchronous operatio n: wait for tcn2ub, ocr2xub, and tcr2xub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency. ? when writing to one of the registers tcnt2, o cr2x, or tccr2x, the valu e is transferred to a temporary register, and latched after two pos itive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination regi ster has taken place, the asynchronous status register ? assr has been implemented. ? when entering power-save or adc noise redu ction mode after having written to tcnt2, ocr2x, or tccr2x, the user must wait unt il the written register has been updated if timer/counter2 is used to wake up the device. othe rwise, the mcu will enter sleep mode before the changes are effective. this is partic ularly important if any of the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the corres ponding ocr2xub bit returns to zero , the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re- entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in do ubt whether the time be fore re-entering power- save or adc noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a. write a value to tccr2x, tcnt2, or ocr2x. b. wait until the correspond ing update busy flag in assr return s to zero. c. enter power-save or a dc noise reduction mode. ? when the asynchronous operation is selected, the 32.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or 168 7593a?avr?02/06 at90usb64/128 wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/coun ter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. ? description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: when the interrupt condit ion is met, the wake up process is started on the following cycle of the timer clock, that is , the timer is always advanced by at least one before the processor can read the counter valu e. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchro nous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phas e of the tosc clock after waking up from power-save mode is essentially unpredictable , as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2x or tccr2x. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 proc essor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor ca n read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 15.9.3 timer/counter2 interrupt mask register ? timsk2 ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable when the ocie2b bit is written to one and the i- bit in the status register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs , i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i- bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs , i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable bit 765432 1 0 ?????ocie2bocie2atoie2timsk2 read/writerrrrrr/w r/wr/w initial value 0 0 0 0 0 0 0 0 169 7593a?avr?02/06 at90usb64/128 when the toie2 bit is written to one and the i- bit in the status register is set (one), the timer/counter2 overflow interr upt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 15.9.4 timer/counter2 interrupt flag register ? tifr2 ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf2b is cleared by writing a logic one to the flag. when the i-bi t in sreg, ocie2b (timer/co unter2 compare match interrupt enable), and ocf2b are set (one), the timer/co unter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, ocf2a is cleared by writing a logic one to the flag. when the i-bi t in sreg, ocie2a (timer/co unter2 compare match interrupt enable), and ocf2a are set (one), the timer/co unter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occu rs in timer/counter2. to v2 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow inter- rupt enable), and tov2 are set (one), the timer/ counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. bit 76543210 ?????ocf2bocf2atov2tifr2 read/writerrrrrr/wr/wr/w initial value00000000 170 7593a?avr?02/06 at90usb64/128 15.10 timer/counter prescaler figure 15-12. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc 2 are disconnected from port c. a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2. the oscillator is optimized for use with a 32.768 khz crystal. apply- ing an external clock source to tosc1 is not recommended. for timer/counter2, t he possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescale r. this allows the user to operate with a predictable prescaler. 15.10.1 general timer/counter control register ? gtccr ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the time r/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written wh en timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescale r has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?general timer/counter control register ? gtccr? on page 100 for a description of the timer/counter synchronization mode. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s tosc1 as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 p srasy clear clk t2 bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ?psra- sy psrsy nc gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 171 7593a?avr?02/06 at90usb64/128 16. output compare modulator (ocm1c0a) 16.1 overview the output compare modulator (ocm) allows generation of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8-bit timer/counter0. for more details about these timer/counters see ?timer/counter0, timer/counter 1, and timer/counter3 pres- calers? on page 99 and ?8-bit timer/counter2 with pwm and asynchronous operation? on page 150 . figure 16-1. output compare modulator, block diagram when the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram ( figure 16-1 ). 16.2 description the output compare unit 1c and output compare unit 2 shares the pb7 port pin for output. the outputs of the output compare units (oc1c a nd oc0a) overrides the normal portb7 register when one of them is enabled (i.e., when comnx1 :0 is not equal to zero). when both oc1c and oc0a are enabled at the same time, th e modulator is autom atically enabled. the functional equivalent schemati c of the modulator is shown on figure 16-2 . the schematic includes part of the timer/counter units and the port b pin 7 output driver circuit. figure 16-2. output compare modulator, schematic oc1c pin oc1c / oc0a / pb7 timer/counter 1 timer/counter 0 oc0a portb7 ddrb7 dq dq pin coma01 coma00 databus oc1c / oc0a/ pb7 com1c1 com1c0 modulator 1 0 oc1c dq oc0a dq ( from waveform generator ) ( from waveform generator ) 0 1 vcc 172 7593a?avr?02/06 at90usb64/128 when the modulator is enabled the type of modulat ion (logical and or or) can be selected by the portb7 register. note that the ddrb7 controls the direction of the port independent of the comnx1:0 bit setting. 16.2.1 timing example figure 16-3 illustrates the modulator in ac tion. in this example the ti mer/counter1 is set to oper- ate in fast pwm mode (non-inverted) and time r/counter0 uses ctc wa veform mode with toggle compare output mode (comnx1:0 = 1). figure 16-3. output compare modulator, timing diagram in this example, timer/counter2 provides the carrier, while the modulating signal is generated by the output compare unit c of the timer/counter1. the resolution of the pwm signal (oc1c) is redu ced by the modulation. the reduction factor is equal to the number of system clock cycles of one period of the carrier (oc0a). in this example the resolution is reduced by a factor of two. the reason for the reduction is illustrated in figure 16-3 at the second and third period of the pb7 output when portb7 equals zero. the period 2 high time is one cycle longer than the period 3 high time, but the result on the pb7 output is equal in both periods. 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o 173 7593a?avr?02/06 at90usb64/128 17. serial peripheral interface ? spi the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the at90usb64/128 and peripheral devices or between several avr devices. the at90usb64/128 spi includes the following features: ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode usart can also be used in master spi mode, see ?usart in spi mode? on page 207. the power reduction spi bit, prspi, in ?power reduction register 0 - prr0? on page 55 on page 50 must be written to zero to enable spi module. figure 17-1. spi block diagram (1) note: 1. refer to figure 1-1 on page 3 , and table 10-6 on page 81 for spi pin placement. the interconnection between master an d slave cpus with spi is shown in figure 17-2 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pu lling low the slave select ss pin of the desired slave. master and spi2x spi2x divider /2/4/8/16/32/64/128 174 7593a?avr?02/06 at90usb64/128 slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to in terchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before commu nication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enab le bit (spie) in the spc r register is set, an interrupt is requested. the master may continue to shift the next byte by wr iting it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been co mpletely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last inco ming byte will be kept in the buffer register for later use. figure 17-2. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direc- tion. this means that bytes to be transmitted ca nnot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequ ency of the spi clock should never exceed f osc /4. shift enable 175 7593a?avr?02/06 at90usb64/128 when the spi is enabled, the data di rection of the mosi, miso, sck, and ss pins is overridden according to table 17-1 . for more details on automatic port overrides, refer to ?alternate port functions? on page 78 . note: 1. see ?alternate functions of port b? on page 81 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_ miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 17-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 176 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 179 7593a?avr?02/06 at90usb64/128 and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 17-3 and figure 17-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determ ine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 17-3 and figure 17-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: 17.1.4 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag table 17-2. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 17-3. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 17-4. relationship between sck an d the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 spif wcol ? ? ? ? ? spi2x spsr read/writerrrrrrrr/w initial value00000000 180 7593a?avr?02/06 at90usb64/128 when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driv en low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardwa re when executing the corresponding interrupt handling vector. alternativel y, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by firs t reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at 90usb64/128 and will a lways read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck freque ncy) will be doubled when the spi is in master mode (see table 17-4 ). this means that the mini mum sck period will be two cpu clock periods. when the spi is configured as sl ave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the at 90usb64/128 is also used for program memory and eeprom downloading or uploading. see page 382 for serial programming and verification. 17.1.5 spi data register ? spdr the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the regist er initiates data transmis sion. reading the regis- ter causes the shift register receive buffer to be read. 17.2 data modes there are four combinations of sck phase and po larity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 17-3 and figure 17-4 . data bits are shifted out and latch ed in on opposite edges of the sck sig- nal, ensuring sufficient time for data signals to st abilize. this is clearly seen by summarizing table 17-2 and table 17-3 , as done below: bit 76543210 msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxundefined 181 7593a?avr?02/06 at90usb64/128 figure 17-3. spi transfer format with cpha = 0 figure 17-4. spi transfer format with cpha = 1 table 17-5. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 182 7593a?avr?02/06 at90usb64/128 18. usart the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communicati on device. the main features are: ? full duplex operation (independent serial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete , tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode . 18.1 overview a simplified block diagram of the usart transmitter is shown in figure 18-1 on page 183 . cpu accessible i/o registers and i/o pins are shown in bold. 183 7593a?avr?02/06 at90usb64/128 figure 18-1. usart block diagram (1) note: 1. see figure 1-1 on page 3 , table 10-12 on page 85 and for usart pin placement. the dashed boxes in the block diagram separate th e three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic consis ts of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmi tter consists of a single write buffer, a serial shift register, parity generator and cont rol logic for handling different serial frame for- mats. the write buffer allows a continuous transf er of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. 18.2 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usartn supports four modes of clock opera tion: normal asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (u mseln = 1), the data direction register parity generator ubrr[h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 184 7593a?avr?02/06 at90usb64/128 for the xckn pin (ddr_xckn) cont rols whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 18-2 shows a block diagram of the clock generation logic. figure 18-2. clock generation logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal si gnal). used for synchronous master operation. f osc xtal pin frequency (system clock). 18.2.1 internal clock generation ? the baud rate generator internal clock generation is used for the asyn chronous and the synchronous master modes of operation. the description in this section refers to figure 18-2 . the usart baud rate register (ubrrn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn va lue each time the counter has counted down to zero or when the ubrrln register is written. a clock is gene rated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator out- put is used directly by the rece iver?s clock and data recovery unit s. however, the recovery units use a state machine that uses 2, 8 or 16 stat es depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. prescaling down-counter /2 ubrr /4 /2 fosc ubrr+1 sync register osc xck pin txclk u2x umsel ddr_xck 0 1 0 1 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector ucpol 185 7593a?avr?02/06 at90usb64/128 table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrhn and ubrrln registers, (0-4095) some examples of ubrrn values for some system clock frequencies are found in table 18-9 on page 204 . 18.2.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. table 18-1. equations for calculating ba ud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 186 7593a?avr?02/06 at90usb64/128 18.2.3 external clock external clocking is used by the synchronous slav e modes of operation. the description in this section refers to figure 18-2 for details. external clock input from the xckn pin is sampled by a synchronization register to minimize the chance of meta-stability. the output from the synchronizati on register must then pass through an edge detector before it can be used by the transmitter and receiver. this process intro- duces a two cpu clock period delay and therefore the maximum external xckn clock frequency is limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefore re commended to add some margin to avoid possible loss of data due to frequency variations. 18.2.4 synchronous clock operation when synchronous mode is used (umseln = 1), th e xckn pin will be used as either clock input (slave) or clock output (master). the depen dency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 18-3. synchronous mode xckn timing. the ucpoln bit ucrsc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 18-3 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and samp led at rising xckn edge. 18.3 frame formats a serial frame is defined to be one character of data bits with synchronizati on bits (start and stop bits), and optionally a pa rity bit for error checking. the u sart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 187 7593a?avr?02/06 at90usb64/128 a frame starts with the start bit followed by the le ast significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with t he most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits . when a complete frame is transmitted, it can be directly followed by a new frame, or the communi cation line can be set to an idle (high) state. figure 18-4 illustrates the possible combinations of th e frame formats. bits inside brackets are optional. figure 18-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt a ll ongoing communication fo r both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbsn) bit. the re ceiver ignores the second stop bit. an fe (f rame error) will theref ore only be detected in the cases where the first stop bit is zero. 18.3.1 parity bit calculation the parity bit is calculated by do ing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the rela tion between the parity bi t and data bits is as follows:: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is locate d between the last data bit and first stop bit of a serial frame. 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 188 7593a?avr?02/06 at90usb64/128 18.4 usart initialization the usart has to be initialized before any communi cation can take place. the initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usag e. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud ra te or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the rece ive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c func- tion that are equal in functionality. the exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. see ?about code examples? on page 8. more advanced initialization rout ines can be made that include frame format as parameters, dis- able interrupts and so on. however, many appl ications use a fixed setting of the baud and control registers, and for these ty pes of applications the initializatio n code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. assembly code example (1) usart_init: ; set baud rate out ubrrhn, r17 out ubrrln, r16 ; enable receiver and transmitter ldi r16, (1< 192 7593a?avr?02/06 at90usb64/128 bits of the data read from the udrn will be ma sked to zero. the usart has to be initialized before the function can be used. note: 1. see ?about code examples? on page 8. the function simply waits for data to be present in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. 18.6.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucs- rnb before reading the low bits from the udrn. this rule applies to the fen, dorn and upen status flags as well. read st atus from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive bu ffer fifo and consequently the txb8n, fen, dorn and upen bits, which all ar e stored in the fifo, will change. the following code example shows a simple usart receive function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 194 7593a?avr?02/06 at90usb64/128 the receive complete (rxcn) flag indicates if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and cons equently the rxcn bit will become zero. when the receive complete interrupt enable (r xcien) in ucsrnb is set, the usart receive complete interrupt will be executed as long as the rxcn flag is set (provi ded that gl obal inter- rupts are enabled). when interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in orde r to clear the rxcn flag, otherwise a new inter- rupt will occur once the inte rrupt routine terminates. 18.6.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by r eading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the erro r flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location change s the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart impl ementations. none of the error flags can genera te interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility wit h future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is fu ll (two characters), it is a new character wait- ing in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility wi th future devices, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 187 and ?parity checker? on page 194 . 18.6.5 parity checker the parity checker is active when the high usart parity mode (upmn1) bit is set. type of par- ity check to be performed (odd or even) is select ed by the upmn0 bit. wh en enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. 195 7593a?avr?02/06 at90usb64/128 the upen bit is set if the nex t character that can be read from the receive buffer had a parity error when received and the parity checking was en abled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 18.6.6 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i .e., the rxenn is set to zero) the receiver will no longer override the normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 18.6.7 flushing the receive buffer the receiver buffer fifo will be fl ushed when the receiver is disa bled, i.e., the buffer will be emptied of its contents. unread data will be los t. if the buffer has to be flushed during normal operation, due to for in stance an error conditi on, read the udrn i/o locati on until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see ?about code examples? on page 8. 18.7 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery l ogic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic sam- ples and low pass filters each incoming bit, ther eby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 18.7.1 asynchronous clock recovery the clock recovery logic synchronizes internal clock to the incoming serial frames. figure 18-5 illustrates the sampling process of th e start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the hor- izontal arrows illustrate the sy nchronization variation due to t he sampling process. note the larger time variation when using the double speed mode (u2xn = 1) of operation. samples denoted zero are samples done when the rxdn line is idle (i.e., no communication activity). assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 197 7593a?avr?02/06 at90usb64/128 figure 18-7. stop bit sampling and ne xt start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 va lue, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority vo ting. for normal speed mode, the fi rst low level sample can be at point marked (a) in figure 18-7 . for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the ear ly start bit detection influences the operational range of the receiver. 18.7.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud ra te of the receiver does not have a similar (see table 18-2 ) base frequency, the receiver will not be abl e to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and pari ty size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data ra te that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest in coming data rate that can be accepted in relation to the receiver baud rate. table 18-2 and table 18-3 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) table 1. r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 198 7593a?avr?02/06 at90usb64/128 the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources fo r the receivers baud rate erro r. the receiver?s system clock (xtal) will always have some minor instabilit y over the supply voltage range and the tempera- ture range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequen cy to get the baud rate wanted. in this case an ubrr value that gives an acceptable low error can be used if possible. 18.8 multi-processor communication mode setting the multi-processor communication m ode (mpcmn) bit in ucsr na enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bu s. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. if the receiver is set up to receive frames that c ontain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. if the receiver is set up for frames with table 18-2. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 18-3. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 199 7593a?avr?02/06 at90usb64/128 nine data bits, then the ninth bit (rxb8n) is us ed for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will receiv e the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. 18.8.1 using mpcmn for an mcu to act as a master mcu, it can us e a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor co mmunication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data fram es until a new address frame is received. the other slave mcus, which still have the mp cmn bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+ 1 character frame formats. this makes full- duplex operation difficult since t he transmitter and receiver uses the same character size set- ting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. do not use read-modify-write in structions (sbi and cbi) to se t or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidentally be cleared when using sbi or cbi instructions. 18.9 usart register description 18.9.1 usart i/o data register n? udrn the usart transmit data buffer register and usart receive data buffer registers share the same i/o address referred to as usart data register or udrn. the transmit data buffer reg- bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 200 7593a?avr?02/06 at90usb64/128 ister (txb) will be the destination for data wri tten to the udrn register location. reading the udrn register location will retu rn the contents of the receiv e data buffer register (rxb). for 5-, 6-, or 7-bit characters the uppe r unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrna register is set. data written to udrn wh en the udren flag is not set, will be ignored by the usart transmit- ter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift regist er when the shift regist er is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo . the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-modify- write instructions (sbi and cbi) on this location. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. 18.9.2 usart control and status register a ? ucsrna ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread dat a). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interr upt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the en tire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag c an generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to re ceive new data. if udren is one, the buffer is empty, and therefore re ady to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indica te that the transmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in th e receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is ze ro when the stop bit of received data is one. always set this bit to ze ro when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two characters), it is a new char acter waiting in the receive shift register, and a bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/writerr/wrrrrr/wr/w initial value00100000 201 7593a?avr?02/06 at90usb64/128 new start bit is detected. this bi t is valid until the receive buffer (udrn) is read . always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usart parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using syn- chronous operation. writing this bit to one will reduce the divisor of th e baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communicati on mode. when the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain address infor- mation will be ignored. the trans mitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 198 . 18.9.3 usart control and status register n b ? ucsrnb ? bit 7 ? rxcien: rx comp lete interrupt enable n writing this bit to one enables interrupt on the rxcn flag. a usart rece ive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enables interrupt on the txcn flag. a usart trans mit complete interrupt will be generated only if the txcien bit is written to one, the glo bal interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 ? udrien: usart data regi ster empty interrupt enable n writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrien bit is written to o ne, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart receiv er. the receiver will override normal port oper- ation for the rxdn pin when enabled. disab ling the receiver will fl ush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enable s the usart transmitter. the trans mitter will override normal port operation for the txdn pin when enabled. the di sabling of the transmitter (writing txenn to bit 7 6 5 4 3 2 1 0 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 202 7593a?avr?02/06 at90usb64/128 zero) will not become effective until ongoing a nd pending transmissions are completed, i.e., when the transmit shift register and transmit buffe r register do not contain data to be trans- mitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bi t in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received char acter when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. 18.9.4 usart control and status register n c ? ucsrnc ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of oper ation of the usartn as shown in table 18-4 .. note: 1. see ?usart in spi mode? on page 207 for full description of the master spi mode (mspim) operation ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter will automatically generate and send t he parity of the transmitted data bits within each frame. the receiver will generate a parity va lue for the incoming data and co mpare it to the upmn setting. if a mismatch is detected, the upen flag in ucsrna will be set. bit 7 6 5 4 3 2 1 0 umseln1 umseln0 upmn1 upmn0 usbsn ucszn1 ucszn0 ucpoln ucsrnc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 18-4. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) table 18-5. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity 203 7593a?avr?02/06 at90usb64/128 ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be in serted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship betwee n data output change and data input sample, and the synchronous clock (xckn). 18.9.5 usart baud rate registers ? ubrrln and ubrrhn ? bit 15:12 ? reserved bits table 18-6. usbs bit settings usbsn stop bit(s) 01-bit 12-bit table 18-7. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 100reserved 101reserved 110reserved 1119-bit table 18-8. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 1514131211109 8 ???? ubrr[11:8] ubrrhn ubrr[7:0] ubrrln 76543210 read/writerrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 204 7593a?avr?02/06 at90usb64/128 these bits are reserved for future use. for compat ibility with future device s, these bit must be written to zero when ubrrh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contains the usart baud rate. the ubrrh contains the four most significant bits, and the ubrrl contains the eight least significant bi ts of the usart baud rate. ongoing transmissions by the transmitter and receiver will be co rrupted if the baud rate is changed. writing ubrrl will tr igger an immediate update of the baud rate prescaler. 18.10 examples of ba ud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the ubrr settings in table 18-9 to table 18-12 . ubrr values which yield an actual baud rate diffe ring less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 197 ). the error values are calculat ed using the following equation: error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = table 18-9. examples of ubrrn settings for commonly used oscillator frequencies baud rate (bps) f osc = 1.0000 mhz f osc = 1.8432 mhz f osc = 2.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 250.2%510.2%470.0%950.0%510.2%1030.2% 4800 120.2%250.2%230.0%470.0%250.2%510.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps 1. ubrr = 0, error = 0.0% 205 7593a?avr?02/06 at90usb64/128 table 18-10. examples of ubrrn settings for commonl y used oscillator frequencies (continued) baud rate (bps) f osc = 3.6864 mhz f osc = 4.0000 mhz f osc = 7.3728 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0. 2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kbps 921.6 kbps 1. ubrr = 0, error = 0.0% 206 7593a?avr?02/06 at90usb64/128 table 18-11. examples of ubrrn settings for commonl y used oscillator frequencies (continued) baud rate (bps) f osc = 8.0000 mhz f osc = 11.0592 mhz f osc = 14.7456 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0. 0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0. 0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0. 0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ? ? 0 0.0% ? ? ? ? 0 -7.8% 1 -7.8% max. (1) 0.5 mbps 1 mbps 691.2 kbps 1.3824 mbps 921.6 kbps 1.8432 mbps 1. ubrr = 0, error = 0.0% 207 7593a?avr?02/06 at90usb64/128 19. usart in spi mode the universal synchronous and asynchronous seri al receiver and transmitter (usart) can be set to a master spi compliant mode of operation. the master spi mode (mspim) has the follow- ing features: ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data transfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operation (fxckmax = fck/2) ? flexible interrupt generation 19.1 overview setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of opera- tion the spi master control logic takes direct control over the us art resources. these resources include the transmitter and receiver sh ift register and buffers, and the baud rate gen- erator. the parity generator and checker, the data and clock recovery logic, and the rx and tx table 18-12. examples of ubrrn settings for commonl y used oscillator frequencies (continued) baud rate (bps) f osc = 16.0000 mhz f osc = 18.4320 mhz f osc = 20.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 0 0.0% 1 0.0% ? ? ? ? ? ? ? ? max. (1) 1 mbps 2 mbps 1.152 mbps 2.304 mbps 1.25 mbps 2.5 mbps 1. ubrr = 0, error = 0.0% 208 7593a?avr?02/06 at90usb64/128 control logic is disabled. the usart rx and tx control logic is replaced by a common spi transfer control logic. ho wever, the pin control logic and interr upt generation logi c is identical in both modes of operation. the i/o register locations are the same in both mo des. however, some of the functionality of the control registers changes when using mspim. 19.2 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal cl ock generation (i.e. mast er operation) is sup- ported. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for th e usart in mspim to operate correc tly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous mas- ter mode. the baud rate or ubrrn setting can therefore be calculated using the same equations, see table 19-1 : note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) 19.3 spi data modes and timing there are four combinations of xckn (sck) phase and polarity with respect to serial data, which are determined by control bits ucphan and ucpol n. the data transfer timing diagrams are shown in figure 19-1 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring sufficient time for data sign als to stabilize. the ucp oln and ucphan function- table 19-1. equations for calculating ba ud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 209 7593a?avr?02/06 at90usb64/128 ality is summarized in table 19-2 . note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. figure 19-1. ucphan and ucpoln data transfer timing diagrams. 19.4 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. when a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame format used by the usart in mspim mode. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoin g communication for both th e receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udrn. a uart transmit com- plete interrupt will then signal that the 16-bit value ha s been shifted out. 19.4.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally cons ists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate independently. for interrupt driven usart opera- table 19-2. ucpoln and ucphan functionality- ucpoln ucphan spi mode lead ing edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 210 7593a?avr?02/06 at90usb64/128 tion, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initializat ion of the xckn output the baud-ra te register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. setting ubrrn to ze ro before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the peri od the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buff er. note that the txcn flag must be cleared bef ore each transmission (before udrn is wri tten) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c func- tion that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 211 7593a?avr?02/06 at90usb64/128 note: 1. see ?about code examples? on page 8. 19.5 data transfer using the usart in mspi mode requires the tr ansmitter to be enabled, i. e. the txenn bit in the ucsrnb register is set to one. when the transmitter is enabled, the normal port operation of the txdn pin is overridden and given the function as the trans mitter's serial output. enabling the receiver is optional and is done by setting the rxenn bit in the uc srnb register to one. when the receiver is enabled, the normal pin opera tion of the rxdn pin is overridden and given the function as the receiver's se rial input. the xckn will in both cases be used as the transfer clock. assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 214 7593a?avr?02/06 at90usb64/128 19.6.3 usart mspim control and status register n b - ucsrnb ? bit 7 - rxcien: rx complete interrupt enable writing this bit to one enables interrupt on the rxcn flag. a usart rece ive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 - txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a usart trans mit complete interrupt will be generated only if the txcien bit is written to one, the glo bal interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 - udrie: usart data register empty interrupt enable writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrie bit is written to one, the glob al interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 - rxenn: receiver enable writing this bit to one enable s the usart receiver in mspim mode. the receiver will override normal port oper ation for the rxdn pin when enabled . disabling the receiver will flush the receive buffer. only enabling the receiver in mspi mode (i.e. setting rxenn=1 and txenn=0) has no meaning since it is the tr ansmitter that contro ls the transfer clock and since only master mode is supported. ? bit 3 - txenn: transmitter enable writing this bit to one enable s the usart transmitter. the trans mitter will override normal port operation for the txdn pin when enabled. the di sabling of the transmitter (writing txenn to zero) will not become effective until ongoing a nd pending transmissions are completed, i.e., when the transmit shift register and transmit buffe r register do not contain data to be trans- mitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2:0 - reserved bits in mspi mode when in mspi mode, these bits ar e reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnb is written. 19.6.4 usart mspim control and status register n c - ucsrnc ? bit 7:6 - umseln1:0: usart mode select bit 7 6 5 4 3 2 1 0 rxcien txcien udrie rxenn txenn - - - ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 1 1 0 bit 76543210 umseln1 umseln0 - - - udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 1 1 0 215 7593a?avr?02/06 at90usb64/128 these bits select the mode of operation of the usart as shown in table 19-3 . see ?usart control and status register n c ? ucsrnc? on page 202 for full description of the normal usart operation. the mspim is enabled wh en both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same write operation where the mspim is enabled. ? bit 5:3 - reserved bits in mspi mode when in mspi mode, these bits ar e reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 - udordn: data order when set to one the lsb of the data word is trans mitted first. when set to zero the msb of the data word is transmitted first. refer to th e frame formats section page 4 for details. ? bit 1 - ucphan: clock phase the ucphan bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 - ucpoln: clock polarity the ucpoln bit sets the polarity of the xc kn clock. the combination of the ucpoln and ucphan bit settings determine th e timing of the data transfer. refer to the spi data modes and timing section page 4 for details. 19.6.5 usart mspim baud rate registers - ubrrnl and ubrrnh the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see ?usart baud rate registers ? ubrrln and ubrrhn? on page 203. 19.7 avr usart mspim vs. avr spi the usart in mspim mode is fully co mpatible with the avr spi regarding: ? master mode timing diagram. ? the ucpoln bit functionality is identical to the spi cpol bit. ? the ucphan bit functionality is identical to the spi cpha bit. ? the udordn bit functionality is identical to the spi dord bit. however, since the usart in mspim mode re uses the usart resources, the use of the usart in mspim mode is somewhat different compar ed to the spi. in addition to differences of the control register bits, and that only master operation is supported by the usart in mspim mode, the following features differ between the two modules: ? the usart in mspim mode includes (double) buffering of the transmitter. the spi has no buffer. table 19-3. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) 216 7593a?avr?02/06 at90usb64/128 ? the usart in mspim mode receiver includes an additional buffer level. ? the spi wcol (write collision) bit is not included in usart in mspim mode. ? the spi double speed mode (spi2x) bit is not included. however, the same effect is achieved by setting ubrrn accordingly. ? interrupt timing is not compatible. ? pin control differs due to the master on ly operation of the usart in mspim mode. a comparison of the usart in mspim mode and the spi pins is shown in table 19-4 on page 216 . table 19-4. comparison of usart in mspim mode and spi pins. usart_mspim spi comment txdn mosi master out only rxdn miso master in only xckn sck (functionally identical) (n/a) ss not supported by usart in mspim 217 7593a?avr?02/06 at90usb64/128 20. 2-wire serial interface 20.1 features ? simple yet powerful and fl exible communication interface, only two bus lines needed ? both master and slave operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode 20.2 2-wire serial in terface bus definition the 2-wire serial interface (twi) is ideally suited for typical microcontroller applications. the twi protocol allows the systems designer to inte rconnect up to 128 differe nt devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hard- ware needed to implement the bus is a single pull- up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 20-1. twi bus interconnection 20.2.1 twi terminology the following definitions are frequently encountered in this section. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 20-1. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. 218 7593a?avr?02/06 at90usb64/128 the power reduction twi bit, prtwi bit in ?power reduction register 0 - prr0? on page 55 must be written to zero to enab le the 2-wire serial interface. 20.2.2 electrical interconnection as depicted in figure 20-1 , both bus lines are connected to the positive supply voltage through pull-up resistors. the bus driver s of all twi-compliant devices are open-drain or open-collector. this implements a wired-and functi on which is essential to the o peration of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices trim-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?spi timing characteristics? on page 405 . two different sets of specifications are presen ted there, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. 20.3 data transfer and frame format 20.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 20-2. data validity 20.3.2 start and stop conditions the master initiates and terminates a data transmission. the trans mission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of t he bus. a special case occurs when a new start condition is issued between a st art and stop condition. this is referred to as a repeated start condition, and is used when the master wis hes to initiate a new transfer without relin- quishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for th e remainder of this datashee t, unless otherwise noted. as sda scl data stable data stable data change 219 7593a?avr?02/06 at90usb64/128 depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. figure 20-3. start, repeated start and stop conditions 20.3.3 address packet format all address packets transmitted on the twi bus are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read opera- tion is to be performed, otherwise a writ e operation should be performed. when a slave recognizes that it is being a ddressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wi shes to transmit the same message to several slaves in the system. when the general call addr ess followed by a write bit is transmitted on the bus, all slaves set up to ackn owledge the general call will pull the sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowle dged the general call. note that transmitting the general call addre ss followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 20-4. address packet format sda scl start stop repeated start stop start sda scl start 12 789 addr msb addr lsb r/w ack 220 7593a?avr?02/06 at90usb64/128 20.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is res ponsible for acknowledgi ng the reception. an acknowledge (ack) is signalled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 20-5. data packet format 20.3.5 combining address and data packets into a transmission a transmission basically consists of a start co ndition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condi- tion, is illegal. note that the wired-anding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the cloc k speed set up by the master is too fast for the slave, or the slave needs extra time for proces sing between the data transmissions. the slave extending the scl low period will not affect t he scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 20-6 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol imple- mented by the application software. figure 20-6. typical data transmission 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 221 7593a?avr?02/06 at90usb64/128 20.4 multi-master bus systems, ar bitration and synchronization the twi protocol allows bus s ystems with several masters. s pecial concerns have been taken in order to ensure that transmis sions will proceed as normal, even if two or more ma sters initiate a transmission at the same time. two pr oblems arise in mu lti-master systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease tran smission when they discover that they have lost the selection process. this selection pr ocess is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. th e fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solv e both these problems. the serial clocks from all masters will be wired-anded, yielding a co mbined clock with a high period equal to the one from the master with the shorte st high period. the low period of the combined clock is equal to the low period of the master with the longest low per iod. note that all ma sters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 20-7. scl synchronization betw een multiple masters arbitration is carried out by all masters cont inuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will cont inue until only one master remains, and this may take many ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period 222 7593a?avr?02/06 at90usb64/128 bits. if several masters are trying to address th e same slave, arbitratio n will continue into the data packet. figure 20-8. arbitration between two masters note that arbitration is not allowed between: ? a repeated start condition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s responsibility to ensure that these illegal arbitr ation conditions never occur. this implies that in multi-master system s, all data transfers must use the same composi- tion of sla+r/w and data packets. in other wo rds: all transmissions must contain the same number of data packets, otherwise the re sult of the arbitration is undefined. 20.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 20-9 . all registers drawn in a thick line are accessible through the avr data bus. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 223 7593a?avr?02/06 at90usb64/128 figure 20-9. overview of the twi module 20.5.1 scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. note that the internal pull-ups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 20.5.2 bit rate generator unit this unit controls the period of scl when oper ating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at l east 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 224 7593a?avr?02/06 at90usb64/128 ? twbr = value of the twi bit rate register. ? twps = value of the prescaler bits in the twi status register. note: twbr should be 10 or higher if the twi operates in master mode. if twbr is lower than 10, the master may produce an incorrect output on sda an d scl for the reminder of the byte. the prob- lem occurs when operating the twi in master mode, sending start + sla + r/w to a slave (a slave does not need to be connected to the bus for the condition to happen). 20.5.3 bus interface unit this unit contains the data and address shif t register (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in additi on to the 8-bit twdr, the bus interface unit also contains a register containing th e (n)ack bit to be transmitted or received. this (n)ack regis- ter is not directly accessible by the application software. however, when re ceiving, it can be set or cleared by manipulating the twi control r egister (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for gene ration and dete ction of start, repeated start, and stop conditions. th e start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as mast er, the arbitration detection hardware continu- ously monitors the transmission trying to determine if arbitration is in proc ess. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 20.5.4 address match unit the address match unit checks if received ad dress bytes match the seven-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge it s address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addresse d by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wakes up the cpu, the twi aborts opera- tion and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down. 20.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requ iring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi sta- tus register (twsr) is updated with a stat us code identifying the event. the twsr only contains relevant status inform ation when the twi interrupt flag is asserted. at all other times, the twsr contains a special stat us code indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before a llowing the twi transmission to continue. scl frequency cpu clock frequency 16 2(twbr) 4 twps ? + ----------------------------------------------------------- = 225 7593a?avr?02/06 at90usb64/128 the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave address or general call. ? after the twi has received a data byte. ? after a stop or repeated start has been received while still addressed as a slave. ? when a bus error has occu rred due to an illegal st art or stop condition. 20.6 twi register description 20.6.1 twi bit rate register ? twbr ? bits 7..0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 223 for calculating bit rates. 20.6.2 twi control register ? twcr the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to th e bus, to generate a receiver acknowledge, to generate a stop condition, and to control haltin g of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempted written to twdr while the regist er is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and tw ie in twcr are set, the mcu will jump to the twi interrupt vector. while the tw int flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automati- cally cleared by hardware when executing the interr upt routine. also note that clearing this flag starts the operation of the twi, so all access es to the twi address register (twar), twi sta- tus register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ac knowledge pulse. if the twea bit is written to one, the ack pulse is generated on the tw i bus if the following conditions are met: bit 76543210 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 226 7593a?avr?02/06 at90usb64/128 1. the device?s own slave add ress has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address re cognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hardware checks if the bu s is available, and generates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected, and then generates a new start cond ition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will g enerate a stop condition on the 2-wire serial bus. when the stop c ondition is executed on the bus, the twsto bit is cleared auto- matically. in slave mode, setting the twsto bit c an be used to recover from an error condition. this will not generate a stop co ndition, but the twi returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleare d by writing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates the twi interface. when twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reserved bit an d will always read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in sreg is set, th e twi interrupt request will be acti- vated for as long as the twint flag is high. 20.6.3 twi status register ? twsr ? bits 7..3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2-wire serial bus. the different status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the pres- bit 76543210 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/writerrrrrrr/wr/w initial value11111000 227 7593a?avr?02/06 at90usb64/128 caler bits to zero when checking the status bits. this makes status checking independent of prescaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. ? bits 1..0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 223 . the value of twps1..0 is used in the equation. 20.6.4 twi data register ? twdr in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data regis- ter cannot be initialized by the user before the first interrupt occurs. th e data in twdr remains stable as long as twint is set. while data is shif ted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case , the contents of twdr is undefined. in the case of a lost bus arbitration, no data is lost in th e transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cann ot access the ack bit directly. ? bits 7..0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire serial bus. 20.6.5 twi (slave) address register ? twar the twar should be loaded with the 7-bit slave address (in the seven most significant bits of twar) to which the twi will respond when progr ammed as a slave transmitter or receiver, and not needed in the master modes. in multim aster systems, twar must be set in masters which can be addressed as slaves by other masters. table 20-2. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 228 7593a?avr?02/06 at90usb64/128 the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a ma tch is found, an interrupt request is generated. ? bits 7..1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. 20.6.6 twi (slave) address mask register ? twamr ? bits 7..1 ? twam: twi address mask the twamr can be loaded with a 7-bit slave addr ess mask. each of the bits in twamr can mask (disable) the corresponding address bit in the twi address register (twar). if the mask bit is set to one then the address match l ogic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 20-10 shows the address match logic in detail. figure 20-10. twi address match logic, block diagram ? bit 0 ? res: reserved bit this bit is reserved and will always read as zero. 20.7 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr to gether with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is clear ed, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the current bit 76543210 twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 addre ss match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 229 7593a?avr?02/06 at90usb64/128 state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 20-11 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanat ion follows later in th is section. a simple code example imple- menting the desired behavior is also presented. figure 20-11. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi ha rdware to transmit a start condition. which value to write is described la ter on. however, it is important that the twint bit is set in the value written. writ ing a one to twint clears the flag. the twi will not start any operation as long as the tw int bit in twcr is set. immediately after the application has cleared twint, the tw i will initiate transmission of the start condition. 2. when the start condition has been transmit ted, the twint flag in twcr is set, and twsr is updated with a status code indica ting that the start condition has success- fully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully trans mitted. if twsr indicates otherwise, the application software might take some s pecial action, like callin g an error routine. assuming that the status code is as expe cted, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is im portant that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. im mediately after the application has cleared twint, the twi will initiate transm ission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indica ting that the address packet has success- fully been sent. the status code will also reflect whether a sl ave acknowledged the packet or not. start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 230 7593a?avr?02/06 at90usb64/128 5. the application software should now examine the value of twsr, to make sure that the address packet was successf ully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an e rror routine. assuming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to tw cr, instructing the twi hardware to transmit the data packet present in twdr. which value to writ e is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cl eared twint, the twi w ill initiate transmission of the data packet. 6. when the data packet has been transmitt ed, the twint flag in twcr is set, and twsr is updated with a status code indicati ng that the data packet has successfully been sent. the status code will also reflec t whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an erro r routine. assuming that the status code is as expected, the application must write a specific value to twcr, inst ructing the twi hardware to transmit a stop condition. which value to wr ite is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cl eared twint, the twi w ill initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows t he principles involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pull ed low until twint is cleared. ? when the twint flag is set, the user must upd ate all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing twcr, th e twint bit should be set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made, for example by using include-files. 231 7593a?avr?02/06 at90usb64/128 table 2. assembly code example c example comments 1 ldi r16, (1< 233 7593a?avr?02/06 at90usb64/128 figure 20-12. data transfer in mast er transmitter mode a start condition is sent by wr iting the following value to twcr: twen must be set to enable the 2-wire serial inte rface, twsta must be written to one to trans- mit a start condition and twint must be written to one to cl ear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 20-3 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the tr ansfer. this is accomplis hed by writing the follow- ing value to twcr: when sla+w have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 20-3 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be written when twint is high. if not, the access will be discarded, and the write collision bit (twwc) will be set in the twcr regis- ter. after updating twdr, the twint bit should be cleared (by writing it to one) to continue the transfer. this is acco mplished by writing the following value to twcr: this scheme is repeated until the last byte ha s been sent and the transfer is ended by generat- ing a stop condition or a repeated start conditio n. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master transmitter device 2 slave receiver device 3 device n sda scl ........ r1 r2 v cc 234 7593a?avr?02/06 at90usb64/128 after a repeated start condition (state 0x10) th e 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode with- out losing control of the bus. table 20-3. status codes for mast er transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmit- ted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmit- ted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free 235 7593a?avr?02/06 at90usb64/128 figure 20-13. formats and states in the master transmitter mode 20.8.2 master receiver mode in the master receiver mode, a number of dat a bytes are received from a slave transmitter (slave see figure 20-14 ). in order to enter a master mode, a start condition must be transmit- ted. the format of the following address packe t determines whether ma ster transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s 236 7593a?avr?02/06 at90usb64/128 figure 20-14. data transfer in ma ster receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the 2-wir e serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. the twi will then test the 2-wire serial bus and gen erate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 20-3 ). in order to enter mr mode, sla+r must be transmitted. this is done by wr iting sla+r to twdr. th ereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+r have been transmitted and an ackno wledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 20-4 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is genera ted by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) th e 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 237 7593a?avr?02/06 at90usb64/128 the master to switch between slaves, master transmitter mode and master receiver mode with- out losing control over the bus. table 20-4. status codes for ma ster receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 238 7593a?avr?02/06 at90usb64/128 figure 20-15. formats and states in the master receiver mode 20.8.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 20-16 ). all the status codes ment ioned in this section assume that the prescaler bits are zero or are masked to zero. figure 20-16. data transfer in slave receiver mode to initiate the slave receiver mode, twar and twcr must be initialized as follows: s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a $58 a r s twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 239 7593a?avr?02/06 at90usb64/128 the upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the tw i will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 20-5 . the slave receiver mode may also be entered if ar bitration is lost while th e twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the tw i will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the 2-wire se rial bus is still monitored and address recognit ion may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clo ck system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its ow n slave address or the general call address by using the 2-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twin t flag is cleared (by writing it to one). further data reception will be carried out as normal, with the avr clocks run- ning as normal. observe that if the avr is set up with a long st art-up time, the scl line may be held low for a long time, blo cking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 240 7593a?avr?02/06 at90usb64/128 table 20-5. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 241 7593a?avr?02/06 at90usb64/128 figure 20-17. formats and states in the slave receiver mode 20.8.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 20-18 ). all the status codes ment ioned in this section assume that the prescaler bits are zero or are masked to zero. figure 20-18. data transfer in slave transmitter mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 242 7593a?avr?02/06 at90usb64/128 to initiate the slave transmitter mode, twar and twcr must be in itialized as follows: the upper seven bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the tw i will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherw ise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 20-6 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transm it the last byte of the trans- fer. state 0xc0 or state 0xc8 will be entere d, depending on whether the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the mast er if it continues the transfer. thus the mast er receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has tran smitted the last byte (twea zero and expect- ing nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clo ck system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its ow n slave address or the general call address by using the 2-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the tw int flag is cleared (by writing it to one). further data tr ansmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is se t up with a long start-up time, the scl line may be held low for a long time, bl ocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x table 20-6. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 243 7593a?avr?02/06 at90usb64/128 figure 20-19. formats and states in the slave transmitter mode 20.8.5 miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 20-7 . 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free table 20-6. status codes for slave transmitter mode s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a 244 7593a?avr?02/06 at90usb64/128 status 0xf8 indicates that no relevant inform ation is available becaus e the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occu rred during a 2-wire serial bus transfer. a bus error occurs when a start or stop condition occu rs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. 20.8.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it w ants to read, requiring the use of the mt mode. subsequently, data must be read from the slave, impl ying the use of the mr mode. t hus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated in a multimaster sys- tem, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data lo cation. such a change in transfe r direction is accomplished by transmitting a repeated start be tween the transmissio n of the address by te and reception of the data. after a repeated start, the mast er keeps ownership of the bus. the following figure shows the flow in this transfer. figure 20-20. combining several twi modes to access a serial eeprom table 20-7. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p 245 7593a?avr?02/06 at90usb64/128 20.9 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simulta- neously by one or more of them. the twi standar d ensures that such situations are handled in such a way that one of the mast ers will be allowed to proceed wit h the transf er, and that no data will be lost in the process. an example of an arbitration situat ion is depicted below, where two masters are trying to transmit data to a slave receiver. figure 20-21. an arbitration example several different scenarios may arise du ring arbitration, as described below: ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the ma sters will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, eith er in the read/write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to no t addressed slave mode or wa it until the bus is free and transmit a new start condition, depending on application software action. ? two or more masters ar e accessing different slaves. in this case, arbitratio n will occur in the sla bits. masters trying to outp ut a one on sda while another mast er outputs a zero will lose the arbitration. masters losing arbi tration in sla will switch to sl ave mode to chec k if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addr essed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on ap plication software action. this is summarized in figure 20-22 . possible status values are given in circles. device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v cc 246 7593a?avr?02/06 at90usb64/128 figure 20-22. possible status codes c aused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 247 7593a?avr?02/06 at90usb64/128 21. usb controller 21.1 features ? support full-speed and low-speed. ? support ping-pong mode (dual bank) ? 832 bytes of dpram. ? 1 endpoint 64 bytes max (default control endpoint), ? 1 endpoints of 256 bytes max, (one or two banks), ? 5 endpoints of 64 bytes max, (one or two banks) 21.2 block diagram the usb controller provides the hardware to interface a usb link to a data flow stored in a dou- ble port memory (dpram). the usb controller requires a 48 mhz 0.25% refer ence clock, which is the output of an internal pll. the pll generates the internal high frequenc y (48 mhz) clock for usb interface, the pll input is generated from an external low-frequency (the crystal oscillator or external clock input pin from xtal1, to satisfy the usb frequency ac curacy and jitter, only t hese sources clock allow proper functionnality of the usb controller). the 48mhz clock is used to generate a 12 mhz full-speed (or 1 mhz low-speed bit clock from the received usb differential data and to transmi t data according to full or low speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block, which is com- pliant with the jitter spec ification of the usb bus. to comply the usb dc characteristics, usb pads (d+ or d-) should be powered within the 3.0 to 3.6v range. as at90usb64/128 can be powered up to 5.5v, an internal regulator can insure the usb pads power supply. 248 7593a?avr?02/06 at90usb64/128 figure 21-1. usb controller blo ck diagram overview 21.3 typical application implementation depending on the usb operating mode (device only, reduced host or otg mode) and target application power supply, the at90usb64/128 requires different hardware typical implementations. figure 21-2. operating modes versus frequency and power-supply cpu usb regulator usb interface pll 24x clk 2mhz clk 48mhz pll clock prescaler on-chip usb dpram dpll clock recovery ucap d- d+ vbus uid uvcc avcc xtal 1 vcc (v) v cc min 0 3.0 3.4 5.5 usb not operationnal usb operationnal without internal regulator usb operationnal with internal regulator 4.5 2.7 max operating frequency (mhz) 8 mhz 16 mhz 2 mhz 249 7593a?avr?02/06 at90usb64/128 21.3.1 device mode 21.3.1.1 bus powered device figure 21-3. typical bus powered application with 5v i/o figure 21-4. typical bus powered application with 3v i/o 21.3.1.2 self powered device figure 21-5. typical self powered application with 3.4v to 5.5v i/o 1? udm udp vbus uvss uid ucap d- d+ vbus uid uvss uvcc avcc dvcc xtal1 xtal2 avss dvss 1? uvss external 3v regulator udm udp vbus uvss uid ucap d- d+ vbus uid uvss uvcc avcc dvcc xtal1 xtal2 avss dvss 250 7593a?avr?02/06 at90usb64/128 figure 21-6. typical bus powered application with 3.0v to 3.4 i/o 21.3.2 host / otg mode figure 21-7. host/otg powered applicati on with 3.0v to 3.4 i/o figure 21-8. host/otg powered application with 5v i/o 1? external 3.4v - 5.5v power supply udm udp vbus uvss uid ucap d- d+ vbus uid uvss uvcc avcc dvcc xtal1 xtal2 avss dvss 1? external 3.0v - 3.4v power supply udm udp vbus uvss uid ucap d- d+ vbus uid uvss uvcc avcc dvcc xtal1 xtal2 avss dvss 251 7593a?avr?02/06 at90usb64/128 21.4 general operating modes 21.4.1 introduction after a hardware reset, the usb controller is di sabled. when enabled, the usb controller has to run the device controller or th e host controller. this is pe rformed using the id detection. ? if the id pin is not connected to ground, the id bit is set by hardware (internal pull up on the uid pad) and the usb device controller is selected. 1? external 3.0v - 3.4v power supply udm udp vbus uvss uid ucap d- d+ vbus uid uvss uvcc avcc dvcc xtal1 xtal2 avss dvss udm udp vbus uvss uid d- d+ vbus uid uvss 1? external 5.0v power suppl y ucap uvcc avcc dvcc xtal1 xtal2 avss dvss uvcon 5v 252 7593a?avr?02/06 at90usb64/128 ? the id bit is cleared by hardware when a low level has been detected on the id pin. the device controller is then disabled and the host controller enabled. the software anyway has to select the mode (host, device) in or der to access to the device controller registers or to the host controller regi sters, which are multiplexed. for example, even if the usb controller has detected a device mode (pin id high), the software shall select the device mode (bit host cleared), otherwise it will a ccess to the host registers. this is also true for the host mode. 21.4.2 power-on and reset the next diagram explains the usb co ntroller main states on power-on: figure 21-9. usb controller states after reset usb controller state after an hardware reset is ?reset?. in this state: ? usbe is not set ? the macro clock is stopped in order to minimize the power consumption (frzclk=1), ? the macro is disabled, ? the pad is in the suspend mode, ? the host and device usb controllers internal states are reset. ? the dpacc bit and the dpadd10:0 field can be set by software. the dpram is not cleared. ? the spdconf bits can be set by software. after setting usbe, the u sb controller enters in the host or in the device state (according to the ip pin). the selected controller is ?idle?. the usb controller can at any time be ?stopped? by clearing usbe. in fact, clearing usbe acts as an hardware reset. 21.4.3 interrupts two interrupts vectors are assigned to usb interface. dev ice reset usbe=0 253 7593a?avr?02/06 at90usb64/128 figure 21-10. usb interrupt system see section 22.18, page 279 and section 23.15, page 299 for more details on the host and device interrupts. usb general & otg interrupt usb device interrupt usb host interrupt usb general interrupt vector endpoint interrupt pipe interrupt usb endpoint/pipe interrupt vector 254 7593a?avr?02/06 at90usb64/128 figure 21-11. usb general interrupt vector sources idte usbcon.1 idti usbint.1 vbusti usbint.0 vbuste usbcon.0 stoi otgint.5 stoe otgien.5 hnperri otgint.4 hnperre otgien.4 roleexi otgint.3 roleexe otgien.3 bcerri otgint.2 bcerre otgien.2 vberri otgint.1 vberre otgien.1 srpi otgint.0 srpe otgien.0 usb general interrupt vector uprsmi udint.6 uprsme udien.6 eorsmi udint.5 eorsme udien.5 wakeupi udint.4 wakeupe udien.4 eorsti udint.3 eorste udien.3 sofi udint.2 sofe udien.2 suspi udint.0 suspe udien.0 hwupe uhien.6 hwupi uhint.6 hsofi uhint.5 hsofe uhien.5 rxrsmi uhint.4 rxrsme uhien.4 rsmedi uhint.3 rsmede uhien.3 rsti uhint.2 rste uhien.2 ddisci uhint.1 ddisce uhien.1 dconni uhint.0 dconne uhien.0 usb device interrupt usb host interrupt usb general interrupt vector asynchronous interrupt source (allows the cpu to wake up from power down mode) 255 7593a?avr?02/06 at90usb64/128 figure 21-12. usb endpoint/pipe interrupt vector sources flerre ueienx.7 overfi uestax.6 underfi uestax.5 nakini ueintx.6 nakine ueienx.6 nakouti ueintx.4 txstpe ueienx.4 rxstpi ueintx.3 txoute ueienx.3 rxouti ueintx.2 rxoute ueienx.2 stalledi ueintx.1 stallede ueienx.1 epint ueint.x endpoint 0 endpoint 1 endpoint 2 endpoint 3 endpoint 4 endpoint 5 endpoint interrupt txini ueintx.0 txine ueienx.0 flerre upien.7 underfi upstax.5 overfi upstax.6 nakedi upintx.6 nakede upien.6 perri upintx.4 perre upien.4 txstpi upintx.3 txstpe upien.3 txouti upintx.2 txoute upien.2 rxstalli upintx.1 rxstalle upien.1 rxini upintx.0 rxine upien.0 flerre upien.7 pipe 0 pipe 1 pipe 2 pipe 3 pipe 4 pipe 5 pipe interrupt usb endpoint/ p interrupt vect o endpoint 6 pipe 6 256 7593a?avr?02/06 at90usb64/128 figure 21-13. usb general and otg cont roller interrupt system there are 2 kind of interrupts: processing (i.e. th eir generation are part of the normal processing) and exception (errors). processing interrupts are generated when: ? id pad detection (insert, remove)( idti) ? vbus plug-in detection (insert, remove) ( vbusti ) ? srp detected( srpi ) ? role exchanged( roleexi ) exception interrupts are generated when: ? drop on vbus detected( vberri ) ? error during the b-connection( bcerri ) ? hnp error( hnperri ) ? time-out detected during suspend mode( stoii ) 21.5 power modes 21.5.1 idle mode in this mode, the cpu core is halted (cpu cloc k stopped). the idle mode is taken whatever the usb controller is running or not. the cpu ?wakes up? on any usb interrupts. 21.5.2 power down in this mode, the oscillator is stopped and halts all the product (cpu and peripherals). the cpu ?wakes up? when: ? the wakeupi interrupt is triggered in the peripher al mode (host cleared), idte usbcon.1 idti usbint.1 vbusti usbint.0 vbuste usbcon.0 stoi otgint.5 stoe otgien.5 hnperri otgint.4 hnperre otgien.4 roleexi otgint.3 roleexe otgien.3 bcerri otgint.2 bcerre otgien.2 vberri otgint.1 vberre otgien.1 srpi otgint.0 srpe otgien.0 usb general & otg interrupt vector asynchronous interrupt source (allows the cpu to wake up from power down mode) 257 7593a?avr?02/06 at90usb64/128 ? the hwupi interrupt is triggered in the host mode (host set). ? the idti interrupt is triggered ? the vbusti interrupt is triggered 21.5.3 freeze clock the firmware has the ability to reduce the power consumption by setting the frzclk bit, which freeze the clock of usb controller. when frzclk is set, it is still possible to access to the fol- lowing registers: ? usbcon, usbsta, usbint ? dpram direct access (dpadd10:0, uxdatx) ? udcon (detach, ...) ?udint ?udien ?uhcon ?uhint ?uhien moreover, when frzclk is set, only th e following interrupts may be triggered: ? wakeupi ?idti ? vbusti ?hwupi 21.6 speed control 21.6.1 device mode when the usb interface is configured in device mode, the speed selection (full speed or low speed) depends on the udp/udm pull-up. udss regist er allows to select an internal pull up on udm (low speed mode) or udp(full speed mode) data lines. udss should be configure before attaching the device. figure 21-14. device mode speed selection r pu detach udcon.0 udp udm r pu lsm udcon.2 ucap usb regulator 258 7593a?avr?02/06 at90usb64/128 21.6.2 host mode when the usb interface is configured in device mode, internal pull down resistors are activated on both udp udm lines and the interfac e detects the type of device connected. 21.7 memory access capability the cpu has the possibility to directly access to the usb internal memory (dpram). the memory access mode is performed using 2 sfr?s: udpaddh and udpaddl. to enter in this mode: ? the usbe bit must be cleared. ? the dpacc bit and the base address dpadd10:0 must be set. even if the usbe bit is cleared, the dpac c bit and dpadd10:0 field can be used by the firmware. then, a read or a write in uedatx (device m ode) or in updatx (host mode) is performed according to dpadd10:0 and the base address dpadd10:0 field is aut omatically increased. the endpoint fifo pointers and the value of the uxnum registers are discarded in this mode. the aim of this functionality is to use the dpram as extra-memory. when using this mode, there is no influence over the usb controller. 21.8 memory management the controller does only support the following memory allocation management: the reservation of a pipe or an endpoint can only be made in the growing order (pipe/endpoint 0 to the last pipe/endpoint). the firmware shall thus configure them in the same order. the reservation of a pipe or an endpoint ?k i ? is done when its alloc bit is set. then, the hard- ware allocates the memory and inse rt it between the pipe/endpoints ?k i-1 ? and ?k i+1 ?. the ?k i+1 ? pipe/endpoint memory ?slides? up and its data is lost. note that the ?k i+2 ? and upper pipe/end- point memory does not slide. clearing a pipe enable (pen) or an endpoint e nable (epen) does not clear neither its alloc bit, nor its configuration (epsize/psize, epbk /pbk). to free its memory, the firmware should endpoint 0 endpoint 1 to n unused [dpaddh - dpaddl] usb dpram 259 7593a?avr?02/06 at90usb64/128 clear alloc. then, the ?k i+1 ? pipe/endpoint memory automatically ?slides? down. note that the ?k i+2 ? and upper pipe/endpoint memory does not slide. the following figure illustrates the allocation and reorganization of the usb memory in a typical example: table 21-1. allocation and reorganization usb memory flow ? first, pipe/endpoint 0 to pipe/endpoint 5 are configured, in the growing order. the memory of each is reserved in the dpram. ? then, the pipe/endpoint 3 is disabled (epen=0), but its memory reservatio n is internally kept by the controller. ? its alloc bit is cleared: the pipe/endpoint 4 ?slides? down, but the pipe/endpoint 5 does not ?slide?. ? finally, if the firmware chooses to reconfigure the pipe/endpoint 3, with a bigger size. the controller reserved the memory after the endpo int 2 memory and automatically ?slide? the pipe/endpoint 4. the pipe/endpoint 5 does not move and a memory conflict appear, in that both pipe/endpoint 4 and 5 use a common area. the data of those endpoints are potentially lost. note that: ? the data of pipe/endpoint 0 are never lost what ever the activation or deactivation of the higher pipe/endpoint. its data is lost if it is deactivated. ? deactivate and reactivate the same pipe/endpoi nt with the same para meters does not lead to a ?slide? of the higher endpoints. for those endpoints, the data are preserved. ? cfgok is set by hardware even in the case that there is a ?conflict? in the memory allocation. 21.9 pad suspend the next figures illustra tes the pad behaviour: ? in the ?idle? mode, the pad is put in low power consumption mode. ? in the ?active? mode, the pad is working. free memory 0 1 2 3 4 5 epen=1 alloc=1 free memory 0 1 2 4 5 epen=0 (alloc=1) free memory 0 1 2 4 5 pipe/endpoints activation pipe/endpoint disable free its memory (alloc=0) free memory 0 1 2 3 (bigger size) 5 pipe/endpoint activatation lost memory 4 conflict 260 7593a?avr?02/06 at90usb64/128 figure 21-15. pad behaviour the suspi flag indicated that a suspend state has been detected on the usb bus. this flag automatically put the usb pad in idle. the detectio n of a non-idle event sets the wakeupi flag and wakes-up the usb pad. moreover, the pad can also be put in the ?idle? mo de if the detach bit is set. it come back in the active mode when the detach bit is cleared. 21.10 otg timers customizing it is possible to refine some otg timers thanks to the otgtcon and otgcon registers ? page=00b: awaitvrise time -out. [otg] chapter 6.6.5.1 ? value=00btime-out is set to 20 ms ? value=01btime-out is set to 50 ms ? value=10btime-out is set to 70ms ? value=11btime-out is set to 100 ms ? page=01b: vbbuspulsing. [otg] chapter 5.3.4 ? value=00btime-out is set to 15 ms idle mode active mode usbe=1 & detach=0 & suspend usbe=0 | detach=1 | suspend suspi suspend detected = usb pad power down clear suspend by software resume = usb pad wake-up clear resume by software wakeupi pad status active power down active 261 7593a?avr?02/06 at90usb64/128 ? value=01btime-out is set to 23 ms ? value=10btime-out is set to 31 ms ? value=11btime-out is set to 40 ms ? page=10b: pdtmoutcnt. [otg] chapter 5.3.2 ? value=00btime-out is set to 93 ms ? value=01btime-out is set to 105 ms ? value=10btime-out is set to 118 ms ? value=11btime-out is set to 131 ms ? page=11b: srpdettmout. [otg] chapter 5.3.3 ? value=00btime-out is set to 10 us ? value=01btime-out is set to 100 us ? value=10btime-out is set to 1 ms ? value=11btime-out is set to 11 ms 21.11 plug-in detection the usb connection is detect ed by the vbus pad, thanks to the following architecture: figure 21-16. plug-in detection input block diagram the control logic of the uvbus pad outputs 2 signals: ? the ?session_valid? signal is active high when the voltage on the uvbus pad is higher or equal to 1.4v. ? the ?va_vbus_valid? signal is active high wh en the voltage on the uvbus pad is higher or equal to 4.4v. in the host mode, the vbus flag fo llows the next hysteresis rule: ? vbus is set when the voltage on the uvbus pad is higher or equal to 4.4 v. ? vbus is cleared when the voltage on the uvbus pad is lower than 1.4 v. in the peripheral mode, the vbus flag follows the next rule: ? vbus is set when the voltage on the uvbus pad is higher or equal to 1.4 v. ? vbus is cleared when the voltage on the uvbus pad is lower than 1.4 v. the vbusti interrupt is triggered at each transition of the vbus flag. vbusti usbint.0 uvbus vbus usbsta.0 vss vdd pad logic logic session_valid va_vbus_valid r pu r pu vbus_pulsing vbus_discharge 262 7593a?avr?02/06 at90usb64/128 21.12 id detection the id pin transition is detected than ks to the following architecture: figure 21-17. id detection input block diagram the id pin can be used to detect the usb mode (peripheral or host) or software selected. this allows the uid pin to be used has general purpose i/o even when usb interface is enable. when the uid pin is selected, by default, (no a-plug or b-plug), the macro is in the peripheral mode (internal pull-up). the idti interrupt is triggered when a a-plug (host) is plugged or unplugged. the interrupt is not triggered when a b-plug (periph) is plugged or unplugged. id detection is independant of usb global interface enable. 21.13 registers description 21.13.1 usb general registers ? 7 ? uimod: usb mode bit this bit has no effect when the uide bit is se t (external uid pin activated). set to enable the usb device mode. clear to enable the usb host mode ? 6 ? uide: uid pin enable set to enable the usb mode selection (periphera l/host) through the uid pin. clear to enable the usb mode selection (p eripheral/host) with uimod bit register. uide should be modified on ly when the usb interface is disabled (usbe bit cleared). ? 5 ? reserved the value read from this bit is always 0. do not set this bit. ? 4 ? uvcone: uvcon pin enable set to enable the uvcon pin control. clear to di sable the uvcon pin control. this bit should be set only when the usb interface is enable. r pu uimod uhwcon.7 uid id usbsta.1 internal pull up vdd uide uhwcon.6 1 0 bit 7 6 5 4 321 0 uimod uide uvcone uvrege uhwcon read/write r/w r/w r r/w r r r r/w initial value 1 0 0 0 0 0 0 0 263 7593a?avr?02/06 at90usb64/128 ? 3-1 ? reserved the value read from these bits is always 0. do not set these bits. ? 0 ? uvrege: usb pad regulator enable set to enable the usb pad regulator. clear to disable the usb pad regulator. ? 7 ? usbe: usb macro enable bit set to enable the usb controller. clear to disabl e and reset the usb controller, to disable the usb transceiver and to disable the usb controller clock inputs. ? 6 ? host: host bit set to enable the host mode. clear to enable the device mode. ? 5 ? frzclk: freeze usb clock bit set to disable the clock inputs (the ?resume detection? is still ac tive). this reduces the power consumption. clear to enable the clock inputs. ? 4 ? otgpade: otg pad enable set to enable the otg pad. clear to disable the otg pad. note that this bit can be set/cleared even if usbe=0 (this allows the vbus detection even if the usb macro is disable). ? 3-2 ? reserved the value read from these bits is always 0. do not set these bits. ? 1 ? idte: id transition interrupt enable bit set this bit to enable the id transition interrupt gen eration. clear this bit to disable the id transi- tion interrupt generation. ? 0 ? vbuste: vbus transition interrupt enable bit set this bit to enable the vbus transition interrupt generation. clear this bit to disable the vbus transition interrupt generation. ? 7-4 - reserved the value read from these bits is always 0. do not set these bits. ? 3 ? speed: speed status flag bit 7 6 5 4 321 0 usbe host frzclk otgpade - - idte vbuste usbcon read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 1 0 0 0 0 0 bit 76543 2 1 0 ----speed idvbususbsta read/writerrrrrrrr initial value00001 0 1 0 264 7593a?avr?02/06 at90usb64/128 this should be read only when the usb controller operates in host mode, in device mode the value read from this bit is underterminate. set by hardware when the contro ller is in full-speed mode. cle ared by hardware when the controller is in low-speed mode. ? 2 ? reserved the value read from this bit is always 0. do not set this bit. ? 1 ? id: iud pin flag the value read from this bit indicates the state of the uid pin. ? 0 ? vbus: vbus flag the value read from this bit indicates the state of the uvbus pin. this bi t can be used in device mode to monitor the usb bus connection state of the appication. see section 21.11, page 261 for more details. 7-2 - reserved the value read from these bits is always 0. do not set these bits. 1 ? idti: d transition interrupt flag set by hardware when a transition (high to low, low to high) has been detected on the uid pin. shall be cleared by software. ? 0 ? vbusti: ivbus transition interrupt flag set by hardware when a transition (high to low, low to high) has been detected on the vbus pad. shall be cleared by software. ? 7 ? dpacc: dpram direct access bit set this bit to directly read the content the dual-port ram (dpr) data through the uedatx or updatx registers. see section 21.7, page 258 for more details. clear this bit for normal operation and access the dpr through the endpoint fifo. ? 6-3 ? reserved the value read from these bits is always 0. do not set these bits. ? 2- 0 ? dpadd10:8: dpram address high bit bit 76543210 ------idtivbustiusbint read/writerrrrrrr/wr/w initial value00000000 bit 76543210 dpacc - - - - dpadd10:8 udpaddh read/write r/w initial value 0 0 0 0 0 0 0 0 265 7593a?avr?02/06 at90usb64/128 dpadd10:8 is the most si gnificant part of dpadd. the least si gnificant part is provided by the udpaddl register. ? 7-0 ? dpadd7:0: dpram address low bit dapdd7:0 is the least si gnificant part of dpadd. the most significant part is provided by the udpaddh register. ? 7-6 - reserved the value read from these bits is always 0. do not set these bits. ? 5 ? hnpreq: hnp request bit set to initiate the hnp when the controller is in the device mode (b). set to accept the hnp when the controller is in the host mode (a). clear otherwise. ? 4 ? srpreq: srp request bit set to initiate the srp when th e controller is in device mode. cleared by hardware when the controller is initiating a srp. ? 3 ? srpsel: srp selection bit set to choose vbus pulsing as srp method. clear to choose data line pulsing as srp method. ? 2 ? vbushwc: vbus hardware control bit set to disable the hardware control over the uvcon pin. clear to enable the hardware control over the uvcon pin. see for more details ? 1 ? vbusreq: vbus request bit set to assert the uvcon pin in order to enabl e the vbus power supply generation. this bit shall be used when the controller is in the host mode. cleared by hardware when vbusrqc is set. ? 0 ? vbusrqc: vbus request clear bit bit 76543210 dpadd7:0 udpaddl read/write initial value00000000 bit 7 6 5 4 3 2 1 0 - - hnpreq srpreq srpsel vbushwc vbusreq vbusrqc otgcon read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 266 7593a?avr?02/06 at90usb64/128 set to deassert the uvcon pin in order to enable the vbus power supply generation. this bit shall be used when the controller is in the host mode. cleared by hardware immediately after the set. ? 7 ? reserved this bit is reserved and always set. ? 6-5 ? page: timer page access bit set/clear to access a special timer register. see section 21.10, page 260 for more details. ? 4-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 ? value: value bit set to initialize the ne w value of the timer. see section 21.10, page 260 for more details. ? 7-6 - reserved the value read from these bits is always 0. do not set these bits. ? 5 ? stoe: suspend time-out error interrupt enable bit set to enable the stoi interrupt. cle ar to disable the stoi interrupt. ? 4 ? hnperre: hnp error interrupt enable bit set to enable the hnperri interrupt. clear to disa ble the hnperri interrupt. ? 3 ? roleexe: role exchan ge interrupt enable bit set to enable the roleexi interrupt. cle ar to disable the roleexi in terrupt. ? 2 ? bcerre: b-connection error interrupt enable bit set to enable the bcerri interrupt. clear to disa ble the bcerri interrupt. ? 1 ? vberre: vbus error interrupt enable bit set to enable the vberri interrupt. cle ar to disable the vberri interrupt. ? 0 ? srpe: srp interrupt enable bit set to enable the srpi interrupt. cle ar to disable the srpi interrupt. bit 7 6 5 4 3 2 1 0 1 page - - value otgtcon read/write r r/w r/w r r r/w r/w r/w initial value 1 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 - - stoe hnperre roleexe bcerre vberre srpe otgien read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 267 7593a?avr?02/06 at90usb64/128 ? 7-6 - reserved the value read from these bits is always 0. do not set these bits. ? 5 ? stoi: suspend time-out error interrupt flag set by hardware when a time-out error (more than 150 ms) has been detected after a suspend. shall be cleared by software. see for more details. ? 4 ? hnperri: hnp error interrupt flag set by hardware when an error has been detected during the protocol. shall be cleared by software. see for more details. ? 3 ? roleexi: role exchange interrupt flag set by hardware when the usb controller has su ccessfully swapped its mode, due to an hnp negotiation: host to device or device to ho st. shall be cleared by software. see for more details. ? 2 ? bcerri: b-connection error interrupt flag set by hardware when an error occur during t he b-connection. shall be cleared by software. ? 1 ? vberri: v-bus error interrupt flag set by hardware when a drop on vbus has been detected. shall be cleared by software. ? 0 ? srpi: srp interrupt flag set by hardware when a srp has been detected. shall be used in the host mode only shall be cleared by software. 21.14 usb software operating modes depending on the usb operating mode, the software should perform some the following operations: power on the usb interface ? power-on usb pads regulator ? wait usb pads regulator ready state ? configure pll interface ? enable pll ? check pll lock ? enable usb interface ? configure usb interface (usb speed, endpoints configuration...) ? wait for usb vbus information connection bit 7654 3 210 - - stoi hnperri roleexi bcerri vberri srpi otgint read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 268 7593a?avr?02/06 at90usb64/128 ? attach usb device power off the usb interface ? detach usb interface ? disable usb interface ? disable pll ? disable usb pad regulator suspending the usb interface ? clear suspend bit ? set usb suspend clock ? disable pll ? be sure to have interrupts enable to exit sleep mode ? make the mcu enter sleep mode resuming the usb interface ? enable pll ? wait pll lock ? clear usb suspend clock ? clear resume information 269 7593a?avr?02/06 at90usb64/128 22. usb device operating modes 22.1 introduction the usb device controller supports full speed and low speed data transfers. in addition to the default control endpoint, it provides six other endp oints, which can be config ured in control, bulk, interrupt or isochronous modes: ? endpoint 0:programmable size fifo up to 64 bytes, default control endpoint ? endpoints 1 programmable size fifo up to 256 bytes in ping-pong mode. ? endpoints 2 to 6: programmable size fifo up to 64 bytes in ping-pong mode. the controller starts in the ?idle? mode. in this mode, the pad consumption is reduced to the minimum. 22.2 power-on and reset the next diagram explains the usb device controller main states on power-on: figure 22-1. usb device controller states after reset the reset state of the device controller is: ? the macro clock is stopped in order to minimize the power consumption (frzclk set), ? the usb device controller internal state is reset (all the registers are reset to their default value. note that detach is set.) ? the endpoint banks are reset ? the d+ or d- pull up are not activated (mode detach) the d+ or d- pull-up will be activated as so on as the detach bit is cleared and vbus is present. the macro is in the ?idle? state after reset with a minimum power consumption and does not need to have the pll activated to enter in this state. the usb device controller can at any time be re set by clearing usbe (disable usb interface). 22.3 speed identification on startup the usb bus reset is managed by the hardware. at the connection, the host makes a reset that can be: at the end of the reset process (full speed or low speed mode), the end of reset interrupt (eorsti) is generated. then the cpu can read th e speed1 bit to know the speed mode of the device. reset idle hw reset usbe=0 270 7593a?avr?02/06 at90usb64/128 22.4 endpoint reset an endpoint can be reset at any time by setting in the uerst register the bit corresponding to the endpoint (eprstx). this resets: ? the internal state machine on that endpoint, ? the rx and tx banks are cleared and their internal pointers are restored, ? the ueintx, uesta0x and uesta1x ar e restored to their reset value. the data toggle field remains unchanged. the other registers remain unchanged. the endpoint configuration remains active and the endpoint is still enabled. the endpoint reset may be associated with a clea r of the data toggle command (rstdt bit) as an answer to the clear_feature usb command. 22.5 usb reset when an usb reset is detected on the usb line, the next operations are performed by the controller: ? all the endpoints are disabled, except the default control endpoint, ? the default control endpoint is reset (see section 22.4, page 270 for more details). ? the data toggle of the default control endpoint is cleared. 22.6 endpoint selection prior to any operation performed by the cpu, the endpoint must first be selected. this is done by: ? clearing epnums. ? setting epnum with the endpoint numb er which will be managed by the cpu. the cpu can then access to the various endpoint registers and data. 22.7 endpoint activation the endpoint is maintained under reset as long as the epen bit is not set. the following flow must be respected in order to activate an endpoint: 271 7593a?avr?02/06 at90usb64/128 figure 22-2. endpoint activation flow: as long as the endpoint is not correctly c onfigured (cfgok cleared), the hardware does not acknowledge the packets sent by the host. cfgok is will not be sent if the endpoint si ze parameter is bigger than the dpram size. a clear of epen acts as an endpoint reset (see sect ion 22.4, page 270 for mo re details). it also performs the next operation: ? the configuration of the endpoint is kept (epsize, epbk, alloc kept) ? it resets the data toggle field. ? the dpram memory associated to the endpoint is still reserved. see section 21.8, page 258 for more details about the memory allocation/reorganization. 22.8 address setup the usb device address is set up according to the usb protocol: ? the usb device, after power-up, responds at address 0 ? the host sends a setup command (set_a ddress(addr)), ? the firmware records that address in uadd, but keep adden cleared, ? the usb device sends an in command of 0 bytes (in 0 zero length packet), ? then, the firmware can enable the usb device address by setting adden. the only accepted address by the controller is the one stored in uadd. adden and uadd shall not be wr itten at the same time. uadd contains the default address 00h after a power-up or usb reset. endpoint activation cfgok=1 error no yes endpoint activated activate the endpoint select the endpoint epen=1 uenum epnum=x test the correct endpoint configuration uecfg1x alloc epsize epbk configure: - the endpoint size - the bank parametrization allocation and reorganization of the memory is made on-the-fly uecfg0x epdir eptype ... configure: - the endpoint direction - the endpoint type - the not yet disable feature 272 7593a?avr?02/06 at90usb64/128 adden is cleared by hardware: ? after a power-up reset, ? when an usb reset is received, ? or when the macro is disabled (usbe cleared) when this bit is cleared, the def ault device address 00h is used. 22.9 suspend, wake-up and resume after a period of 3 ms during which the usb line wa s inactive, the controller switches to the full- speed mode and triggers (if enabled) the suspi (suspend) interrupt. the firmware may then set the frzclk bit. the cpu can also, depending on software architecture, enter in the idle mode to lower again the power consumption. there are two ways to recover from the ?suspend? mode: ? first one is to clear the frzclk bit. this is possible if the cpu is not in the idle mode. ? second way, if the cpu is ?idle?, is to en able the wakeupi interrupt (wakeupe set). then, as soon as an non-idle signal is seen by the controller, the wakeupi in terrupt is triggered. the firmware shall then clear the frzclk bit to restart the transfer. there are no relationship be tween the suspi inte rrupt and the wakeupi interrupt: the wake- upi interrupt is triggered as soon as there are non-idle patterns on the data lines. thus, the wakeupi interrupt can occurs even if the controller is not in the ?suspend? mode. when the wakeupi interrupt is tri ggered, if the suspi in terrupt bit was already set, it is cleared by hardware. when the suspi interrupt is trigge red, if the wakeupi interrupt bit was already set, it is cleared by hardware. 22.10 detach the reset value of the detach bit is 1. it is possible to re-enumerate a device, si mply by setting and clearing the detach bit. ? if the usb device controller is in full-speed mode, setting detach will disconnect the pull-up on the d+ or d- pad (depending on full or low speed mode selected). then, clearing detach will connect the pull-up on the d+ or d- pad. figure 22-3. detach a device in full-speed: en=1 d + uvref d - detach, then attach en=1 d + uvref d - 273 7593a?avr?02/06 at90usb64/128 22.11 remote wake-up the ?remote wake-up? (or ?upstream resume?) reque st is the only operati on allowed to be sent by the device on its own initiative. anyway, to do that, the device should first have received a device_remote_wakeup re quest from the host. ? first, the usb controller must have detected the ?suspend? state of the line: the remote wake-up can only be sent after a suspi interrupt has been triggered. ? the firmware has then the ability to set rm wkup to send the ?ups tream resume? stream. this will automatically be done by the controlle r after 5ms of inacti vity on the usb line. ? when the controller starts to send the ?upstream resume?, the uprsmi interrupt is triggered (if enabled). if suspi was set, suspi is cleared by hardware. ? rmwkup is cleared by hardware at the end of the ?upstream resume?. ? if the controller detects a good ?end of resume? signal from the host, an eorsmi interrupt is triggered (if enabled). 22.12 stall request for each endpoint, the stall management is performed using 2 bits: ? stallrq (enable stall request) ? stallrqc (disable stall request) ? stalledi (stall sent interrupt) to send a stall handshake at the next request, t he stallrq request bit has to be set. all fol- lowing requests will be handshak?ed with a stall until the stallrqc bit is set. setting stallrqc automa tically clears the stallrq bit. the stallrqc bit is also immedi- ately cleared by hardware after being set by software. thus, the firmware will ne ver read this bit as set. each time the stall handshake is sent, the stal ledi flag is set by the usb controller and the epintx interrupt will be triggered (if enabled). the incoming packets will be discard ed (rxouti and rwal will not be set). the host will then send a command to reset the st all: the firmware just has to set the stall- rqc bit and to reset the endpoint. 22.12.1 special consideration for control endpoints a setup request is always ack?ed. if a stall request is set for a control endpoint and if a setup request occurs, the setup request has to be ack?ed and the stallrq request and stalledi sent flags are automati- cally reset (rxsetupi set, txin cleared, stalled cleared, txini cleared...). this management simplifies the enumeration process management. if a command is not sup- ported or contains an error, the firmware set t he stall request flag and can return to the main task, waiting for the next setup request. this function is compliant with the chapter 8 test from pmtc that send extra status for a get_descriptor. the firmware se ts the stall request just after receiving the status. all extra status will be automatically st all?ed until the ne xt setup request. 274 7593a?avr?02/06 at90usb64/128 22.12.2 stall handshake and retry mechanism the retry mechanism has priority over the stall handshake. a stall hands hake is sent if the stallrq request bit is set and if there is no retry required. 22.13 control endpoint management a setup request is always ack?ed. when a new setup packet is received, the rxstpi inter- rupt is triggered (if enabled). the rxouti interrupt is not triggered. the fifocon and rwal fields are irrelevant with control endpoints. the firmware shall thus never use them on that endpoints . when read, their value is always 0. control endpoints are managed by the following bits: ? rxstpi is set when a new setup is received. it shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank . ? rxouti is set when a new out data is rece ived. it shall be cleared by firmware to acknowledge the packet and to clear the endpoint bank . ? txini is set when the bank is ready to accept a new in packet. it shall be cleared by firmware to send the packet and to clear the endpoint bank . control endpoints should not be managed by in terrupts, but only by polling the status bits. 22.13.1 control write the next figure shows a control wr ite transaction. during the stat us stage, the controller will not necessary send a nak at the first in token: ? if the firmware knows the exact number of descr iptor bytes that must be read, it can then anticipate on the status stage and send a zlp for the next in token, ? or it can read the bytes and poll nakini, which tells that all the bytes have been sent by the host, and the transaction is now in the status stage. setup rxstpi rxouti txini usb line hw sw out hw sw out hw sw in in nak sw data setup status 275 7593a?avr?02/06 at90usb64/128 22.13.2 control read the next figure shows a control read transaction. the usb controller has to manage the simulta- neous write requests from the cpu and the usb host: a nak handshake is always generated at the first status stage command. when the controller detect the status stage, a ll the data writen by the cpu are erased, and clearing txini has no effects. the firmware checks if the transmission is complete or if the reception is complete. the out retry is always ack?ed. this reception: - set the rxouti flag (received out data) - set the txini flag (data sen t, ready to accept new data) software algorithm: set transmit ready wait (transmit complete or receive complete) if receive complete, clear flag and return if transmit complete, continue once the out status stage has been received, the usb controller waits for a setup request. the setup request have priority over any other request and has to be ack?ed. this means that any other flag should be cleared and the fifo reset when a setup is received. warning: the byte counter is reset when the out zero length packet is received. the firm- ware has to take care of this. 22.14 out endpoint management out packets are sent by the host. all the data c an be read by the cpu, which acknowledges or not the bank when it is empty. 22.14.1 overview the endpoint must be configured first. each time the current bank is full, the rxouti and the fifocon bits are set. this triggers an interrupt if the rxoute bit is set. the firmwa re can acknowledge the usb interrupt by clearing the rxouti bit. the firmware read the data and clear the fifocon bit in order to free the cur- rent bank. if the out endpoint is composed of multiple banks, clearing the fifocon bit will setup rxstpi rxouti txini usb line hw sw in hw sw in out out nak sw sw hw wr enable host wr enable cpu data setup status 276 7593a?avr?02/06 at90usb64/128 switch to the next bank. the rxouti and fi focon bits are then updated by hardware in accordance with the status of the new bank. rxouti shall always be clea red before clearing fifocon. the rwal bit always reflects the state of the current bank. this bit is set if the firmware can read data from the bank, and cleared by hardware when the bank is empty. 22.14.2 detailed description 22.14.2.1 the data are read by the cpu, following the next flow: ? when the bank is filled by the host, an endpoint interrupt ( epintx) is trigge red, if enabled (rxoute set) and rxouti is set. the cpu c an also poll rxouti or fifocon, depending on the software architecture, ? the cpu acknowledges the interrupt by clearing rxouti, ? the cpu can read the number of byte (n) in the current bank (n=byct), ? the cpu can read the data from the current bank (?n? read of uedatx), ? the cpu can free the bank by clearing fifocon when all the data is read, that is: ? after ?n? read of uedatx, ? as soon as rwal is cleared by hardware. if the endpoint uses 2 banks, the second one can be filled by the host wh ile the current one is being read by the cpu. then, when the cpu clear fifocon, the next bank may be already ready and rxouti is set immediately. out data (to bank 0) ack rxouti fifocon hw out data (to bank 0) ack hw sw sw sw example with 1 out data bank read data from cpu bank 0 out data (to bank 0) ack rxouti fifocon hw out data (to bank 1) ack sw sw example with 2 out data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1 nak 277 7593a?avr?02/06 at90usb64/128 22.15 in endpoint management in packets are sent by the usb device controller, upon an in request from the host. all the data can be written by the cpu, which acknowledg e or not the bank when it is full.overview the endpoint must be configured first. the txini bit is set by hardware when the current bank becomes free. this triggers an interrupt if the txine bit is set. the fifo con bit is set at the same time . the cpu writes into the fifo and clears the fifocon bit to allow the usb cont roller to send the data. if the in endpoint is composed of multiple banks, th is also switches to the next da ta bank. the txini and fifocon bits are automatically updated by hardware regarding the status of the next bank. txini shall always be cleared before clearing fifocon. the rwal bit always reflects the state of the current bank. this bit is set if the firmware can write data to the bank, and cleared by hardware when the bank is full. 22.15.1 detailed description the data are written by the cp u, following the next flow: ? when the bank is empty, an endpoint interrupt ( epintx) is triggered, if enabled (txine set) and txini is set. the cpu can also poll tx ini or fifocon, depending the software architecture choice, ? the cpu acknowledges the interrupt by clearing txini, ? the cpu can write the data into th e current bank (write in uedatx), ? the cpu can free the bank by clearing fifocon when all the data are written, that is: in data (bank 0) ack txini fifocon hw example with 1 in data bank write data from cpu bank 0 example with 2 in data banks sw sw sw sw in in data (bank 0) ack txini fifocon write data from cpu bank 0 sw sw sw sw in data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 nak 278 7593a?avr?02/06 at90usb64/128 ? after ?n? write into uedatx ? as soon as rwal is cleared by hardware. if the endpoint uses 2 banks, the second one can be read by the host while the current is being written by the cpu. then, when the cpu clears fifocon, the next bank may be already ready (free) and txini is set immediately. 22.15.1.1 abort an ?abort? stage can be produced by the host in some situations: ? in a control transaction: zlp data out received during a in stage, ? in an isochronous in transaction: zlp data ou t received on the out endpoint during a in stage on the in endpoint ?... the killbk bit is used to kill the last ?written? ba nk. the best way to manage this abort is to per- form the following operations: table 22-1. abort flow 22.16 isochronous mode for isochronous in endpoints, it is possible to automatically switch the banks on each start of frame (sof). this is done by setting isosw. the cpu has to fill the bank of the endpoint; the bank switching will be automatic as soon as a sof is seen by the hardware. a clear of fifocon does not ha ve any effects in this mode. in the case that a sof is missing (noise on usb pad, ...), the controller will automatically build internally a ?pseudo? start of frame and the bank switching is made. the sofi interrupt is trig- gered and the frame number fnum10:0 is increased. 22.16.1 underflow an underflow can occur during in stage if the host attempts to read a bank which is empty. in this situation, the underf i interrupt is triggered. endpoint abort abort done abort is based on the fact that no banks are busy, meaning that nothing has to be sent. disable the txini interrupt. endpoint reset nbusybk =0 yes clear ueienx. txine no killbk=1 killbk=1 yes kill the last written bank. wait for the end of the procedure. no 279 7593a?avr?02/06 at90usb64/128 an underflow can also occur during out stage if the host send a packet while the banks are already full. typically, he cpu is not fast enough. the packet is lost. it is not possible to have underflow error during out stage, in the cpu side, since the cpu should read only if the bank is ready to give data (rxouti=1 or rwal=1) 22.16.2 crc error a crc error can occur during out stage if the u sb controller detects a bad received packet. in this situation, the stalledi interrupt is triggered. this does not prevent the rxouti interrupt from being triggered. 22.17 overflow in control, isochronous, bulk or interrupt endpoi nt, an overflow can occur during out stage, if the host attempts to write in a ba nk that is too small for the packet. in this situation, the overfi interrupt is triggered (if enabled). the packet is hacknowledged and the rxouti interrupt is also triggered (if enabled). the bank is filled with the fi rst bytes of the packet. it is not possible to have overflow error duri ng in stage, in the cpu side, since the cpu should write only if the bank is ready to access data (txini=1 or rwal=1). 22.18 interrupts the next figure shows all the interrupts sources: figure 22-4. usb device controlle r interrupt system there are 2 kind of interrupts: processing (i.e. th eir generation are part of the normal processing) and exception (errors). processing interrupts are generated when: ? vbus plug-in detection (insert, remove)( vbusti ) ? upstream resume( uprsmi ) ? end of resume( eorsmi ) ? wake up( wakeupi ) ? end of reset (speed initialization)( eorsti ) uprsmi udint.6 uprsme udien.6 eorsmi udint.5 eorsme udien.5 wakeupi udint.4 wakeupe udien.4 eorsti udint.3 eorste udien.3 sofi udint.2 sofe udien.2 suspi udint.0 suspe udien.0 usb device interrupt 280 7593a?avr?02/06 at90usb64/128 ? start of frame( sofi , if fncerr=0) ? suspend detected after 3 ms of inactivity( suspi ) exception interrupts are generated when: ? crc error in frame number of sof( sofi , fncerr=1) figure 22-5. usb device controller en dpoint interrupt system processing interrupts are generated when: ? ready to accept in data( epintx , txini=1) ? received out data( epintx , rxouti=1) ? received setup( epintx , rxstpi=1) exception interrupts are generated when: ? stalled packet( epintx , stalledi=1) ? crc error on out in isochronous mode( epintx , stalledi=1) ? overflow in isochronous mode( epintx , overfi=1) ? underflow in isochronous mode( epintx , underfi=1) ? nak in sent( epintx , nakini=1) ? nak out sent( epintx , nakouti=1) epint ueint.x endpoint 0 endpoint 1 endpoint 2 endpoint 3 endpoint 4 endpoint 5 endpoint interrupt endpoint 6 flerre ueienx.7 overfi uestax.6 underfi uestax.5 nakini ueintx.6 nakine ueienx.6 nakouti ueintx.4 txstpe ueienx.4 rxstpi ueintx.3 txoute ueienx.3 rxouti ueintx.2 rxoute ueienx.2 stalledi ueintx.1 stallede ueienx.1 txini ueintx.0 txine ueienx.0 281 7593a?avr?02/06 at90usb64/128 22.19 registers 22.19.1 usb device general registers ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2 - lsm - usb device low speed mode selection when configured usb is configured in device mo de, this bit allows to select the usb the usb low speed or full speed mod. clear to select full speed mode (d+ internal pull- up will be activate with the attach bit will be set) . set to select low spee d mode (d- internal pu ll-up will be activate with the attach bit will be set). this bit has no effect when the usb interface is configured in host mode. ? 1- rmwkup - remote wake-up bit set to send an ?upstream-resume? to the host for a remote wake-up. cleared by hardware . clearing by software has no effect. see section 22.11, page 273 for more details. ? 0 - detach - detach bit set to physically detach de device (disconnect internal pull-up on d+ or d-). clear to reconnect the device. see section 22.10, page 272 for more details. ?7 - reserved the value read from this bits is always 0. do not set this bit. ? 6 - uprsmi - upstream resume interrupt flag set by hardware when the usb controller is sending a resume signal called ?upstream resume?. this triggers an u sb interrupt if uprsme is set. shall be cleared by software (usb clocks must be enabled before) . setting by software has no effect. ? 5 - eorsmi - end of resume interrupt flag set by hardware when the usb controller detec ts a good ?end of resume? signal initiated by the host. this triggers an u sb interrupt if eorsme is set. bit 76543 2 1 0 ----- lsm rmwkup detach udcon read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 1 bit 76543210 - uprsmi eorsmi wakeupi eorsti sofi - suspi udint read/write initial value00000000 282 7593a?avr?02/06 at90usb64/128 shall be cleared by software. se tting by software has no effect. ? 4 - wakeupi - wake-up cpu interrupt flag set by hardware when the usb controller is re-activated by a filtered non-idle signal from the lines (not by an upstream resume). this triggers an interrup t if wakeupe is set. shall be cleared by software (usb clock inputs must be enabled before). setting by software has no effect. see section 22.9, page 272 for more details. ? 3 - eorsti - end of reset interrupt flag set by hardware when an ?end of reset? has been detected by the usb cont roller. this triggers an usb interrupt if eorste is set. shall be cleared by software. se tting by software has no effect. ? 2 - sofi - start of frame interrupt flag set by hardware when an usb ?start of frame? pid (sof) has been detected (every 1 ms). this triggers an usb inte rrupt if sofe is set.. ?1 - reserved the value read from this bits is always 0. do not set this bit ? 0 - suspi - suspend interrupt flag set by hardware when an usb ?suspend? ?idle bus for 3 frame periods: a j state for 3 ms) is detected. this triggers an usb interrupt if suspe is set. shall be cleared by software. se tting by software has no effect. see section 22.9, page 272 for more details. the interrupt bits are set even if their corresponding ?enable? bits is not set. ?7 - reserved the value read from this bits is always 0. do not set this bit. ? 6 - uprsme - upstream re sume interrupt enable bit set to enable the uprsmi interrupt. clear to disable the uprsmi interrupt. ? 5 - eorsme - end of resume interrupt enable bit set to enable the eorsmi interrupt. clear to disable the eorsmi interrupt. ? 4 - wakeupe - wake-up cpu interrupt enable bit set to enable the wakeupi interrupt. bit 76543210 - uprsme eorsme wakeupe eorste sofe - suspe udien read/write initial value 0 0 0 0 0 0 0 0 283 7593a?avr?02/06 at90usb64/128 clear to disable the wakeupi interrupt. ? 3 - eorste - end of reset interrupt enable bit set to enable the eors ti interrupt. this bi t is set after a reset. clear to disable the eorsti interrupt. ? 2 - sofe - start of frame interrupt enable bit set to enable the sofi interrupt. clear to disable the sofi interrupt. ?1 - reserved the value read from this bits is always 0. do not set this bit ? 0 - suspe - suspend interrupt enable bit set to enable t he suspi interrupt. clear to disable the suspi interrupt. ? 7 - adden - address enable bit set to activate the uadd (usb address). cleared by hardware . clearing by software has no effect. see section 22.8, page 271 for more details. ? 6-0 - uadd6:0 - usb address bits load by software to configure the device address. . ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 - fnum10:8 - frame number upper flag set by hardware. these bits are the 3 msb of t he 11-bits frame number information. they are provided in the last received sof packet. fnum is updated if a corrupted sof is received. bit 76543210 adden uadd6:0 udaddr read/write w r/w r/w r/w r/w r/w r/w r/w initial val- ue 00000000 bit 76543 2 1 0 ----- fnum10:8 udfnumh read/writerrrrr r r r initial value00000 0 0 0 284 7593a?avr?02/06 at90usb64/128 ? frame number lower flag set by hardware. these bits are the 8 l sb of the 11-bits frame number information. ? 7-5 - reserved the value read from these bits is always 0. do not set these bits. ? 4 - fncerr -frame number crc error flag set by hardware when a corrupted frame number in start of frame packet is received. this bit and the sofi interrupt are updated at the same time. ? 3-0 - reserved the value read from these bits is always 0. do not set these bits. 22.19.2 usb device endpoint registers ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 - epnum2:0 endpoint number bits load by software to select the number of the endpoint which shall be accessed by the cpu. see section 22.6, page 270 for more details. epnum = 111b is forbidden. bit 76543210 fnum7:0 udfnuml read/writerrrrrrrr initial value00000000 bit 76543210 - - - fncerr - - - - udmfn read/w rite r initial value 00000000 bit 76543210 - - - - - epnum2:0 uenum read/writerrrrrr/wr/wr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 - eprst6 eprst5 eprst4 eprst 3 eprst2 eprst1 eprst0 uerst read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 285 7593a?avr?02/06 at90usb64/128 ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-0 - eprst6:0 - endpoint fifo reset bits set to reset the selected endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. see section 22.4, page 270 for more information then, cleared by software to complete the reset operation and start using the endpoint. ? 7-6 - reserved the value read from these bits is always 0. do not set these bits. ? 5 - stallrq - stall request handshake bit set to request a stall answer to the host for the next handshake. cleared by hardware when a new setup is received. clearin g by software has no effect. see section 22.12, page 273 for more details. ? 4 - stallrqc - stall request clear handshake bit set to disable the stall handshake mechanism. cleared by hardware immediately after the set. clearing by software has no effect. see section 22.12, page 273 for more details. 3 ? rstdt - reset data toggle bit set to automatically clear the data toggle sequence: for out endpoint: the next received packet will have the data toggle 0. for in endpoint: the next packet to be sent will have the data toggle 0. cleared by hardware instantaneously. the firmware does not have to wait that the bit is cleared. clearing by software has no effect. ?2 - reserved the value read from these bits is always 0. do not set these bits. ?1 - reserved the value read from these bits is always 0. do not set these bits. ? 0 - epen - endpoint enable bit set to enable the endpoint according to the devic e configuration. endpoi nt 0 shall always be enabled after a hardware or usb reset and participate in the device configuration. clear this bit to disable the endpoint. see section 22.7, page 270 for more details. bit 76543210 - - stallrq stallrqc rstdt - - epen ueconx read/write r r w w w r r r/w initial value 0 0 0 0 0 0 0 0 286 7593a?avr?02/06 at90usb64/128 ? 7-6 - eptype1:0 - endpoint type bits set this bit according to the endpoint configuration: 00b: control10b: bulk 01b: isochronous11b: interrupt ?5-4 - reserved the value read from these bits is always 0. do not set these bits. ? 3-2 - reserved for test purpose the value read from these bits is always 0. do not set these bits. ?1 - reserved the value read from this bits is always 0. do not set this bit. ? 0 - epdir - endpoint direction bit set to configure an in direction for bulk, interrupt or isochronous endpoints. clear to configure an out direction for bulk , interrupt, isochronous or control endpoints. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-4 - epsize2:0 - endpoint size bits set this bit according to the endpoint size: 000b: 8 bytes100b: 128 bytes 001b: 16 bytes101b: 256 bytes 010b: 32 bytes110b: 512 bytes 011b: 64 bytes111b: reserved. do not use this configuration. ? 3-2 - epbk1:0 - endpoint bank bits set this field according to the endpoint size: 00b: one bank 01b: double bank 1xb: reserved. do not use this configuration. bit 76543210 eptype1:0 - - - - - epdir uecfg0x read/writer/wr/wrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 - epsize2:0 epbk1:0 alloc - uecfg1x read/write r r/w r/w r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 287 7593a?avr?02/06 at90usb64/128 ? 1 - alloc - endpoint allocation bit set this bit to allocate the endpoint memory. clear to free the endpoint memory. see section 22.7, page 270 for more details. ?0 - reserved the value read from these bits is always 0. do not set these bits. ? 7 - cfgok - configuration status flag set by hardware when the endpoint x size paramet er (epsize) and the bank parametrization (epbk) are correct compared to the max fifo capacity and the max number of allowed bank. this bit is updated when the bit alloc is set. if this bit is cleared, the user should reprogram the uecf g1x register with correct epsize and epbk values. ? 6 - overfi - overflow error interrupt flag set by hardware when an overflow error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section 22.16, page 278 for more details. shall be cleared by software. se tting by software has no effect. ? 5 - underfi - flow error interrupt flag set by hardware when an underflow error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section 22.16, page 278 for more details. shall be cleared by software. se tting by software has no effect. ? 4 - zlpseen - zero length packet seen (bit / flag) set by hardware, as soon as a zlp has been filtered during a transfer. shall be cleared by the software. se tting by software has no effect. ? 3-2 - dtseq1:0 - data toggle sequencing flag set by hardware to indicate the pid data of the current bank: 00b data0 01b data1 1xb reserved. for out transfer, this value indicates the last data toggle received on the current bank. bit 76543210 cfgok overfi underfi zlpseen dtseq1:0 nbusybk1:0 uesta0x read/write r r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 288 7593a?avr?02/06 at90usb64/128 for in transfer, it indicates the to ggle that will be used for the next packet to be se nt. this is not relative to the current bank. ? 1-0 - nbusybk1:0 - busy bank flag set by hardware to indicate the number of busy bank. for in endpoint, it indicates the number of busy ba nk(s), filled by the user , ready for in transfer. for out endpoint, it indicates the number of busy bank(s) filled by out transaction from the host. 00b all banks are free 01b 1 busy bank 10b 2 busy banks 11b reserved. ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2 - ctrldir - control direction (flag, and bit for debug purpose) set by hardware after a setup packet, and gives the direction of the following packet: - 1 for in endpoint - 0 for out endpoint. can not be set or cleared by software. ? 1-0 - currbk1:0 - current bank (all en dpoints except cont rol endpoint) flag set by hardware to indicate the number of the current bank: 00b bank0 01b bank1 1xb reserved. can not be set or cleared by software. ? 7 - fifocon - fifo control bit for out and setup endpoint: bit 76543 2 10 - - - - - ctrldir currbk1:0 uesta1x read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 fifocon nakini rwal nakouti rxstp i rxouti stalledi txini ueintx read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 289 7593a?avr?02/06 at90usb64/128 set by hardware when a new out message is stored in the current bank, at the same time than rxout or rxstp. clear to free the current bank and to switch to the following bank. setting by software has no effect. for in endpoint: set by hardware when the current bank is free, at the same time than txin. clear to send the fifo data and to switch th e bank. setting by software has no effect. ? 6 - nakini - nak in received interrupt flag set by hardware when a nak handshake has been s ent in response of a in request from the host. this triggers an usb in terrupt if nakine is sent. shall be cleared by software. se tting by software has no effect. ? 5 - rwal - read/write allowed flag set by hardware to signal: - for an in endpoint: the current bank is not full i.e. the firmware can pus h data into the fifo, - for an out endpoint: the current bank is not empt y, i.e. the firmware c an read data from the fifo. the bit is never set if stallrq is set, or in case of error. cleared by hardware otherwise. this bit shall not be used for the control endpoint. ? 4 - nakouti - nak out re ceived interrupt flag set by hardware when a nak handshake has been sent in response of a out/ping request from the host. this triggers an u sb interrupt if nakoute is sent. shall be cleared by software. se tting by software has no effect. ? 3 - rxstpi - received setup interrupt flag set by hardware to signal that the current bank contains a new valid setup packet . an inter- rupt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. this bit is inactive (cleared) if the endpoint is an in endpoint. ? 2 - rxouti / killbk - rece ived out data interrupt flag set by hardware to signal that the current bank contains a new packet. an interrupt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. kill bank in bit set this bit to kill the last written bank. cleared by hardware when th e bank is killed. clearing by software has no effect. see page 278 for more details on the abort. 290 7593a?avr?02/06 at90usb64/128 ? 1 - stalledi - stalledi interrupt flag set by hardware to signal that a stall handshak e has been sent, or that a crc error has been detected in a out isochronous endpoint. shall be cleared by software. se tting by software has no effect. ? 0 - txini - transmitter ready interrupt flag set by hardware to signal that th e current bank is free and can be filled. an interr upt (epintx) is triggered (if enabled). shall be cleared by software to handshake the interrupt. setting by software has no effect. this bit is inactive (cleared) if the endpoint is an out endpoint. ? 7 - flerre - flow error interrupt enable flag set to enable an endpoint interrupt (epintx) when overfi or underfi are sent. clear to disable an endpoint interrupt (epi ntx) when overfi or underfi are sent. ? 6 - nakine - nak in interrupt enable bit set to enable an endpoint interr upt (epintx) when nakini is set. clear to disable an endpoint interr upt (epintx) when nakini is set. ?5 - reserved the value read from these bits is always 0. do not set these bits. ? 4 - nakoute - nak out interrupt enable bit set to enable an endpoint interr upt (epintx) when nakouti is set. clear to disable an endpoint interr upt (epintx) when nakouti is set. ? 3 - rxstpe - received set up interrupt enable flag set to enable an endpoint interrupt (epintx) when rxstpi is sent. clear to disable an endpoint interrup t (epintx) when rxstpi is sent. ? 2 - rxoute - received out data interrupt enable flag set to enable an endpoint interrupt (epintx) when rxouti is sent. clear to disable an endpoint interrup t (epintx) when rxouti is sent. ? 1 - stallede - stalle d interrupt enable flag set to enable an endpoint interrupt (epintx) when stalledi is sent. clear to disable an endpoint interrup t (epintx) when stalledi is sent. ? 0 - txine - transmitter re ady interrupt enable flag set to enable an endpoint interrupt (epintx) when txini is sent. bit 76543210 flerre nakine - nakoute rxstpe rxoute stallede txine ueienx read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 291 7593a?avr?02/06 at90usb64/128 clear to disable an endpoint interr upt (epintx) when txini is sent. ? 7-0 - dat7:0 -data bits set by the software to read/write a byte fr om/to the endpoint fifo selected by epnum. ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 - byct10:8 - byte count (high) bits set by hardware. this field is the msb of the byte count of the fifo endpoint. the lsb part is provided by the uebclx register. ? 7-0 - byct7:0 - byte count (low) bits set by the hardware. byct10:0 is: - (for in endpoint) increased after each writi ng into the endpoint and decremented after each byte sent, - (for out endpoint) increased after each byte sent by the host, and decremented after each byte read by the software. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-0 - epint6:0 - endpoint interrupts bits set by hardware when an interrupt is triggered by the ueintx register and if the corresponding endpoint interrupt enable bit is set. bit 76543210 dat d7 dat d6 dat d5 dat d4 dat d3 dat d2 dat d1 dat d0 uedatx read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 1 0 - - - - - byct d10 byct d9 byct d8 uebchx read/writerrrrr r r r initial value00000 0 0 0 bit 76543210 byct d7 byct d6 byct d5 byct d4 byct d3 byct d2 byct d1 byct d0 uebclx read/writerrrrrrrr initial value00000000 bit 76543210 - epint d6 epint d5 epint d4 epint d3 epint d2 epint d1 epint d0 ueint read/writerrrrrrrr initial value00000000 292 7593a?avr?02/06 at90usb64/128 cleared by hardware when the interrupt source is served. 293 7593a?avr?02/06 at90usb64/128 23. usb host operating modes 23.1 pipe description for the usb host controller, the term of pipe is used instead of endpoint for the usb device controller. a host pipe corresponds to a device endpoint, as described in the usb specification: figure 23-1. pipes and endpoints in a usb system in the usb host controller, a pipe will be associated to a device endpoint, considering the device configuration descriptors. 23.2 detach the reset value of the detach bit is 1. thus, the firmware has the responsibility of clearing this bit before switching to the host mode (host set). 23.3 power-on and reset the next diagram explains the usb host controller main states on power-on: figure 23-2. usb host controller states after reset host ready host idle device disconnection 294 7593a?avr?02/06 at90usb64/128 usb host controller state after an hardware reset is ?reset?. when the u sb controller is enabled and the usb host controller is selected, the usb cont roller is in ?idle? state. in this state, the usb host controller waits for the device connection, with a minimum power consumption . the usb pad should be in idle mode. the macro does not need to have the pll activated to enter in ?host ready? state. the host controller enters in su spend state when the usb bus is in suspend state, i.e. when the host controller doesn?t generate t he start of frame. in this stat e, the usb consumption is mini- mum. the host controller exits to the suspend stat e when starting to generate the sof over the usb line. 23.4 device detection a device is detected by the usb controller when the usb bus if diffe rent from d+ and d- low. in other words, when the usb host controller dete cts the device pull-up on the d+ line. to enable this detection, the host controller has to pr ovide the vbus power supply to the device. the device disconnection is detected by the usb host controller when th e usb idle correspond to d+ and d- low on the usb line. 23.5 pipe selection prior to any operation performed by the cpu, the pipe must first be selected. this is done by: ? clearing pnums. ? setting pnum with the pipe number which will be managed by the cpu. the cpu can then access to the various pipe registers and data. 23.6 pipe configuration the following flow must be respected in order to activate a pipe: 295 7593a?avr?02/06 at90usb64/128 figure 23-3. pipe activation flow: once the pipe is activated (epen set) and, the hardware is ready to send requests to the device. when configured (cfgok = 1), only the pipe token (ptoken) and the polling interval for inter- rupt pipe can be modified. a control type pipe supports only 1 bank. an y other value will lead to a configuration error (cfgok = 0). a clear of pen will reset the configuration of the pipe. all the corresponding pipe registers are reset to there re set values. please refers to the memo ry management chapter for more details. note: the firmware has to configure the defa ult control pipe with th e following parameters: ? type: control ? token: setup ? data bank: 1 ? size: 64 bytes the firmware asks for 8 bytes of the device descriptor sending a get_descriptor request. these bytes contains the maxpacketsize of the device default control endpoint and the firm- ware re-configures the size of the default control pipe with this size parameter. pipe activ ation upconx penable=1 upcfg0x ptype ptoken pepnum cfgok=1 error no yes upcfg2x intfrq (interrupt only) pipe activ ated and f reezed upcfg1x psize pbk cfgmem enable the pipe select the pipe type: * type (control , bulk, interrupt ) * token (in, out , setup) * endpoint number configure the pipe memory: * pipe size * number of banks configure the polling interval for interrupt pipe 296 7593a?avr?02/06 at90usb64/128 23.7 usb reset the usb controller sends a usb reset when the firmware set the reset bit. the rsti bit is set by hardware when the usb reset has been sent. this triggers an interrupt if the rste has been set. when a usb reset has been sent, all the pipe configuration and the memory allocation are reset. the general host interrupt enable register is left unchanged. if the bus was previously in suspend mode (sof en = 0), the usb controller automatically switches to the resume mode (hwupi is set) and the sofen bit is set by hardware in order to generate sof immediately after the usb reset. 23.8 address setup once the device has answer to the first host requests with the default address (0), the host assigns a new address to the device. the host controller has to send a usb reset to the device and perform a set address control request, with the ne w address to be used by the device. this control request ended, the firmware write the new address in to the uhaddr register. all following requests, on every pipes, will be performed using this new address. when the host controller send a usb reset, the uhaddr register is reset by hardware and the following host requests will be performed using the default address (0). 23.9 remote wake-up detection the host controller enters in suspend mode when clearing the sofen bit. no more start of frame is sent on the usb bus and the usb device enters in suspend mode 3ms later. the device awakes the host controller by sending an upstream resume (remote wake-up feature). the host controller detects a non-idle state on the usb bus and set the hwupi bit. if the non-idle correspond to an upstream resume (k state), the rxrsmi bit is set by hardware. the firmware has to generate a downstream resume within 1ms and for at least 20ms by setting the resume bit. once the downstream resume has been generate d, the sofen bit is automatically set by hard- ware in order to generate sof immediately after the usb resume. 23.10 usb pipe reset the firmware can reset a pipe using the pipe rese t register. the configuration of the pipe and the data toggle remains unchanged. only the bank management and the status bits are reset to their initial values. to completely reset a pipe, the firmware has to disable and then enable the pipe. 23.11 pipe data access in order to read or to write into the pipe fifo, the cpu selects the pipe number with the upnum register and performs read or writ e action on the updatx register. host ready host suspend sofe=1 or hwup=1 sofe=0 297 7593a?avr?02/06 at90usb64/128 23.12 control pipe management a control transaction is composed of 3 phases: ? setup ? data (in or out) ? status (out or in) the firmware has to change the token for each phase. the initial data toggle is set for the corresponding token (only for control pipe): ? setup: data0 ? out: data1 ? in: data1 (expected data toggle) 23.13 out pipe management the pipe must be configured and not frozen first. note: if the firmware decides to switch to suspen d mode (clear sofen) even if a bank is ready to be sent, the usb controller will automatical ly exit from suspend mode and the bank will be sent. the txout bit is set by hardware when the curr ent bank becomes free. this triggers an inter- rupt if the txoute bit is set. the fifocon bit is set at the same time. the cpu writes into the fifo and clears the fifocon bit to allow the usb controller to send the data. 298 7593a?avr?02/06 at90usb64/128 if the out pipe is composed of multiple banks, this also switches to the next data bank. the txout and fifocon bits are autom atically updated by hardware re garding the status of the next bank. 23.14 in pipe management the pipe must be configured first. when the host requires data from the device, the firmware has to determine first the in mode to use using the inmode bit: ? inmode = 0. the inrqx register is taken in account. the host controller will perform (inrqx+1) in requests on the selected pipe be fore freezing the pipe. this mode avoids to have extra in requests on a pipe. ? inmode = 1. the usb controller will perform infini te in request until th e firmware freezes the pipe. the in request gener ation will start when the firm ware clear the pfreeze bit. out data (bank 0) ack txout fifocon hw example with 1 out data bank write data from cpu bank 0 example with 2 out data banks sw sw sw sw out out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw out data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 example with 2 out data banks out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw write data from cpu bank 1 sw hw write data from cpu bank0 out data (bank 1) ack 299 7593a?avr?02/06 at90usb64/128 each time the current bank is full, the rxin and the fifocon bits are set. this triggers an inter- rupt if the rxine bit is set. the firmware c an acknowledge the usb interrupt by clearing the rxin bit. the firmware read t he data and clear the fifocon bit in order to free the current bank. if the in pipe is composed of multiple banks, clearing the fifocon bit will switch to the next bank. the rxin and fifocon bits are then updated by hardware in accordance with the status of the new bank. 23.14.1 crc error (isochronous only) a crc error can occur during in stage if the usb controller detects a bad received packet. in this situation, the stalledi/crcerri interrupt is triggered. this does not prevent the rxini interrupt from being triggered. 23.15 interrupt system in data (to bank 0) ack rxin fifocon hw in data (to bank 0) ack hw sw sw sw example with 1 in data bank read data from cpu bank 0 in data (to bank 0) ack rxin fifocon hw in data (to bank 1) ack sw sw example with 2 in data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1 300 7593a?avr?02/06 at90usb64/128 figure 23-4. usb host controlle r interrupt system figure 23-5. usb device controller pipe interrupt system 23.16 registers hwupe uhien.6 hwupi uhint.6 hsofi uhint.5 hsofe uhien.5 rxrsmi uhint.4 rxrsme uhien.4 rsmedi uhint.3 rsmede uhien.3 rsti uhint.2 rste uhien.2 ddisci uhint.1 ddisce uhien.1 dconni uhint.0 dconne uhien.0 usb host interrupt flerre upien.7 underfi upstax.5 overfi upstax.6 nakedi upintx.6 nakede upien.6 perri upintx.4 perre upien.4 txstpi upintx.3 txstpe upien.3 txouti upintx.2 txoute upien.2 rxstalli upintx.1 rxstalle upien.1 rxini upintx.0 rxine upien.0 flerre upien.7 pipe 0 pipe 1 pipe 2 pipe 3 pipe 4 pipe 5 pipe interrupt pipe 6 301 7593a?avr?02/06 at90usb64/128 23.16.1 general usb host registers ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2 - resume - send usb resume set this bit to generate a usb resume on the usb bus. cleared by hardware wh en the usb resume has been sent. cl earing by software has no effect. ? 1 - reset - send usb reset set this bit to generate a usb reset on the usb bus. cleared by hardware when the usb reset has been sent. clearing by software has no effect. refer to the usb reset se ction for more details. ? 0 - sofen - start of frame generation enable set this bit to generate sof on the usb bus. clear this bit to disable the sof generation and to leave the usb bus in idle state. ?7 - reserved the value read from these bits is always 0. do not set these bits. ?6 - hwup host wake-up interrupt set by hardware when a non-idle state is detected on the usb bus. shall be clear by software to acknowledge the interrupt. setting by software has no effect. ? 5 - hsofi - host start of frame interrupt set by hardware when a sof is issued by the ho st controller. this triggers a usb interrupt when hsofe is set. shall be cleared by software to acknowledge the interrupt. setting by so ftware has no effect. ? 4 - rxrsmi - upstream re sume received interrupt set by hardware when an upstream resume has been received from the device. shall be cleared by software. se tting by software has no effect. bit 76543210 ----- resume reset sofen uhcon read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 - hwup hsof rxrsmi rsmedi rsti ddisci dconni uhint read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 302 7593a?avr?02/06 at90usb64/128 ? 3 - rsmedi - downstream resume sent interrupt set by hardware when a downstream resume has been sent to the device. shall be cleared by software. se tting by software has no effect. ? 2 - rsti - usb reset sent interrupt set by hardware when a usb reset has been sent to the device. shall be cleared by software. se tting by software has no effect. ? 1 - ddisci device di sconnection interrupt set by hardware when the device has been removed from the usb bus. shall be cleared by software. se tting by software has no effect. ? 0 - dconni - device connection interrupt set by hardware when a new device has been connected to the usb bus. shall be cleared by software. se tting by software has no effect. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6 - hwupe - host wake-up interrupt enable set this bit to enable hwup interrupt. clear this bit to disable hwup interrupt. ? 5 - hsofe - host start of frame interrupt enable set this bit to enable hsof interrupt. clear this bit to di sable hsof interrupt. ? 4 - rxrsme -upstream resume received interrupt enable set this bit to enable the rxrsmi interrupt. clear this bit to disabl e the rxrsmi interrupt. ? 3 - rsmede - downstream re sume sent interrupt enable set this bit to enable the rsmedi interrupt. clear this bit to disabl e the rsmedi interrupt. ? 2 - rste - usb reset sent interrupt enable set this bit to enabl e the rsti interrupt. clear this bit to disa ble the rsti interrupt. bit 7654 321 0 hwupe hsofe rxrsme rsmede rste ddisce dconne uhien read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 303 7593a?avr?02/06 at90usb64/128 ? 1 - ddisce - device disconnection interrupt enable set this bit to enabl e the ddisci interrupt. clear this bit to disable the ddisci interrupt. ? 0 - dconne - device connection interrupt enable set this bit to enable the dconni interrupt. clear this bit to disable the dconni interrupt. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-0 - haddr6:0 - usb host address these bits contain the address of the usb device. ? 7-4 - reserved the value read from these bits is always 0. do not set these bits. ? 3-0 - fnum10:8 - frame number the value contained in this register is the current sof number. this value can be modified by software. ? 7-0 - fnum7:0 - frame number the value contained in this register is the current sof number. this value can be modified by software. bit 76543210 haddr6 haddr5 haddr4 haddr3 haddr2 haddr1 haddr0 haddr6 uhaddr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 2 1 0 - - - - - fnum10 fnum9 fnum8 uhfnumh read/writerrrrr r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 uhfnuml read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 304 7593a?avr?02/06 at90usb64/128 ? 7-0 - flen7:0 - frame length the value contained the data frame length transmited. 23.16.2 usb host pipe registers ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 - pnum2:0 - pipe number select the pipe using this register. the usb host registers ended by a x correspond then to this number. this number is used for the usb contro ller following the value of the pnumd bit. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6 - p6rst - pipe 6 reset set this bit to 1 and reset this bit to 0 to reset the pipe 6. ? 5 - p5rst - pipe 5 reset set this bit to 1 and reset this bit to 0 to reset the pipe 5. ? 4 - p4rst - pipe 4 reset set this bit to 1 and reset this bit to 0 to reset the pipe 4. ? 3 - p3rst - pipe 3 reset set this bit to 1 and reset this bit to 0 to reset the pipe 3. ? 2 - p2rst - pipe 2 reset set this bit to 1 and reset this bit to 0 to reset the pipe 2. bit 76543210 flen7 flen6 flen5 flen4 flen3 flen2 flen1 flen0 uhflen read/writerrrrrrrr initial value00000000 bit 76543 2 1 0 pnum2 pnum1 pnum0 upnum read/write rw rw rw initial value00000 0 0 0 bit 76543210 - p6rst p5rst p4rst p3rst p2rst p1rst p0rst uprst read/write rw rw rw rw rw rw rw initial value00000000 305 7593a?avr?02/06 at90usb64/128 ? 1 - p1rst - pipe 1 reset set this bit to 1 and reset this bit to 0 to reset the pipe 1. ? 0 - p0rst - pipe 0 reset set this bit to 1 and reset this bit to 0 to reset the pipe 0. ?7 - reserved the value read from this bit is always 0. do not set this bit. ? 6 - pfreeze - pipe freeze set this bit to freeze the pipe requests generation. clear this bit to enable the pipe request generation. this bit is set by hardware when: - the pipe is not configured - a stall handshake has been received on this pipe - an error occurs on the pipe (perr = 1) - (inrq+1) in requests have been processed this bit is set at 1 by hardware after a pipe reset or a pipe enable. ? 5 - inmode - in request mode set this bit to allow the usb contro ller to perform infinite in requests when the pipe is not frozen. clear this bit to perform a pre-defined number of in requests. this number is stored in the uin- rqx register. ?4 - reserved the value read from this bit is always 0. do not set this bit. ? 3 - rstdt - reset data toggle set this bit to reset the data toggle to its initial value fo r the current pipe. cleared by hardware when proceed. clearing by software has no effect. ?2 - reserved the value read from these bits is always 0. do not set these bits. ?1 - reserved the value read from these bits is always 0. do not set these bits. ? 0 - pen - pipe enable set to enable the pipe. bit 76543210 - pfreeze inmode - rstdt - - pen upconx read/write rw rw rw rw initial value 0 0 0 0 0 0 0 0 306 7593a?avr?02/06 at90usb64/128 clear to disable and reset the pipe. ? 7-6 - ptype1:0 - pipe type select the type of the pipe: - 00: control - 01: isochronous - 10: bulk - 11: interrupt ? 5-4 - ptoken1:0 - pipe token select the token to associate to the pipe - 00: setup - 01: in - 10: out - 11: reserved ? 3-0 - pepnum3:0 - pipe endpoint number set this field according to the pipe configuration. set the number of the endpoint targeted by the pipe. this value is from 0 and 15. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-4 - psize2:0 - pipe size select the size of the pipe: - 000: 8 - 001: 16 - 010: 32 - 011: 64 - 100: 128 - 101: 256 bit 76543210 ptype1 ptype0 ptoken1 ptoken0 pepnum3 pepnum2 pepnum1 pepnum0 upcfg0x read/write rw rw rw rw rw rw rw rw initial value00000000 bit 7 6 5 4 3 2 1 0 - psize2:0 pbk1:0 alloc - upcfg1x read/write r rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 307 7593a?avr?02/06 at90usb64/128 - 110: 512 - 111: 1024 ? 3-2 - pbk1:0 - pipe bank select the number of bank to declare for the current pipe. - 00: 1 bank - 01: 2 banks - 10: invalid - 11: invalid ? alloc configure pipe memory set to configure the pipe memo ry with the characteristics. clear to update the memory allocation. refer to the memory management chapter for more details. 7 - reserved the value read from these bits is always 0. do not set these bits. ? 7 - intfrq7:0 - interrupt pipe request frequency these bits are the maximum value in millisecond of the pulling period fo r an interr upt pipe. this value has no effect for a non-interrupt pipe. ? 7 - cfgok - configure pipe memory ok set by hardware if the required memory configuration has been successfully performed. cleared by hardware when the pipe is disabled. the usb reset and the reset pipe have no effect on the configuration of the pipe. ? 6 - overfi - overflow set by hardware when a the current pipe has received more data than the maximum length of the current pipe. an interrupt is tr iggered if the flerre bit is set. shall be cleared by software. se tting by software has no effect. ? 5 - underfi - underflow bit 76543210 intfrq7 intfrq6 intfrq5 intfrq4 intfrq3 intfrq2 intfrq1 intfrq0 upcfg2x read/writerwrwrwrwrwrwrwrw initial value00000000 bit 76543210 cfgok overfi underfi - dtseq1:0 nbusybk upstax read/writerrwrw rrrr initial value00000000 308 7593a?avr?02/06 at90usb64/128 set by hardware when a transaction underflow occu rs in the current isochronous or interrupt pipe. the pipe can?t send the data flow required by the device. a zlp will be sent instead. an interrupt is triggered if the flerre bit is set. shall be cleared by software. se tting by software has no effect. note: the host controller has to send a out packet, but the bank is empty. a zlp will be sent and the underfi bit is set underflow for interrupt pipe: ?4 - reserved the value read from these bits is always 0. do not set these bits. ? 3-2 - dtseq1:0 - toggle sequencing flag set by hardware to indicate the pid data of the current bank: 00b data0 01b data1 1xb reserved. for out pipe, this value indicates the next data toggle that will be sent . this is not relative to the current bank. for in pipe, this value indicates the last data toggle received on the current bank. ? 1-0 - nbusybk1:0 - busy bank flag set by hardware to indicate the number of busy bank. for out pipe, it indicates the number of busy ba nk(s), filled by the user, ready for out transfer. for in pipe, it indicates the number of busy ba nk(s) filled by in transaction from the device. 00b all banks are free 01b 1 busy bank 10b 2 busy banks 11b reserved. ? 7-0 - inrq7:0 - in request number before freeze enter the number of in transactions before the usb controller freezes the pipe. the usb con- troller will perform (inrq+1) in requests before to freeze the pipe . this counter is automatically decreased by 1 each time a in request has been successfully performed. bit 76543210 inrq7 inrq6 inrq5 inrq4 inrq 3 inrq2 inrq1 inrq0 upinrqx read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 bit 76543210 - counter1:0 crc16 timeout pid datapid datatgl uperrx read/write rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 309 7593a?avr?02/06 at90usb64/128 ? 7-6 - reserved the value read from these bits is always 0. do not set these bits. ? 5 - counter1:0 - error counter this counter is increased by the usb controller each time an error occurs on the pipe. when this value reaches 3, the pipe is automatically frozen. clear these bits by software. ? 4 - crc16 - crc16 error set by hardware when a crc16 error has been detected. shall be cleared by software. se tting by software has no effect. ? 3 - timeout - time-out error set by hardware when a time-out error has been detected. shall be cleared by software. se tting by software has no effect. ? 2 - pid - pid error set by hardware when a pid error has been detected. shall be cleared by software. se tting by software has no effect. ? 1 - datapid - data pid error set by hardware when a data pid error has been detected. shall be cleared by software. se tting by software has no effect. ? 0 - datatgl - bad data toggle set by hardware when a data toggle error has been detected. shall be cleared by software. se tting by software has no effect. ? 7 - fifocon - fifo control for out and setup pipe: set by hardware when the current bank is free, at the same time than txout or txstp. clear to send the fifo data and to switch th e bank. setting by software has no effect. for in pipe: set by hardware when a new in message is stored in the current bank, at the same time than rxin. bit 765432 1 0 fifocon nakedi rwal perri txstpi txouti rxstalli rxini upintx read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 310 7593a?avr?02/06 at90usb64/128 clear to free the current bank and to switch to the following bank. setting by software has no effect. ? 6 - nakedi - nak handshake received set by hardware when a nak has been received on the current bank of the pipe. this triggers an interrupt if the nakede bit is set in the upienx register. shall be clear to handshake the interrup t. setting by software has no effect. ? 5 - rwal - read/write allowed out pipe: set by hardware when the firmware can write a new data into the pipe fifo. cleared by hardware when the current pipe fifo is full. in pipe: set by hardware when the firmware can read a new data into the pipe fifo. cleared by hardware when the current pipe fifo is empty. this bit is also cleared by hardware when the rxstall or the perr bit is set ? 4 - perri -pipe error set by hardware when an error occurs on the current bank of the pipe. this triggers an interrupt if the perre bit is set in the upienx register. refers to the uperrx register to determine the source of the error. automatically cleared by hardware when the error source bit is cleared. ? 3 - txstpi - setup bank ready set by hardware when the current setup bank is free and can be filled. this triggers an inter- rupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. ? 2 - txouti -out bank ready set by hardware when the current out bank is fr ee and can be filled. this triggers an interrupt if the txoute bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. ? 1 - rxstalli / crcerr - stall received / isochronous crc error set by hardware when a stall handshake has been received on the current bank of the pipe. the pipe is automatically frozen. this triggers an interrupt if th e rxstalle bit is set in the upi- enx register. shall be cleared to handshake the interrupt. setting by software has no effect. for isochronous pipe: set by hardware when a crc error occurs on the current bank of the pipe. this triggers an inter- rupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. ? 0 - rxini - in data received 311 7593a?avr?02/06 at90usb64/128 set by hardware when a new usb message is stor ed in the current bank of the pipe. this trig- gers an interrupt if the rxine bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by software has no effect. ? 7 - flerre - flow error interrupt enable set to enable the overfi and underfi interrupts. clear to disable the overfi and underfi interrupts. ? 6 - nakede -nak handshake received interrupt enable set to enable t he nakedi interrupt. clear to disable th e nakedi interrupt. ?5 - reserved the value read from these bits is always 0. do not set these bits. ? 4 - perre -pipe error interrupt enable set to enable t he perri interrupt. clear to disable the perri interrupt. ? 3 - txstpe - setup bank ready interrupt enable set to enable the txstpi interrupt. clear to disable the txstpi interrupt. ? 2 - txoute - out bank ready interrupt enable set to enable the txouti interrupt. clear to disable the txouti interrupt. ? 1 - rxstalle - stall received interrupt enable set to enable the rxstalli interrupt. clear to disable the rxstalli interrupt. ? 0 - rxine - in data re ceived interrupt enable set to enable t he rxini interrupt. clear to disable the rxini interrupt. bit 7 6 5 4 3 2 1 0 flerre nakede - perre txstpe txoute rxstalle rxine upienx read/write rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 bit 76543210 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 updatx read/write rw rw rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 312 7593a?avr?02/06 at90usb64/128 ? 7-0 - pdat7:0 - pipe data bits set by the software to read/write a byte from/to the pipe fifo selected by pnum. ? 7-3 - reserved the value read from these bits is always 0. do not set these bits. ? 2-0 - pbyct10:8 - byte count (high) bits set by hardware. this field is the msb of the byte count of the fifo endpoint. the lsb part is provided by the upbclx register. ? 7-0 - pbyct7:0 - byte count (low) bits set by the hardware. pbyct10:0 is: - (for out pipe) increased after each writing into the pipe and decremented after each byte sent, - (for in pipe) increased after each byte received by the host, and decremented after each byte read by the software. ?7 - reserved the value read from these bits is always 0. do not set these bits. ? 6-0 - pint6:0 - pipe interrupts bits set by hardware when an interrupt is triggered by the upintx register and if the corresponding endpoint interrupt enable bit is set. cleared by hardware when the interrupt source is served. bit 76543 2 1 0 - - - - - pbyct10 pbyct9 pbyct8 upbchx read/write r r r initial value 0 0 0 0 0 0 0 0 bit 76543210 pbyct7 pbyct6 pbyct5 pbyct4 pbyct3 pbyct2 pbyct1 pbyct0 upbclx read/writerrrrrrrr initial value00000000 bit 76543210 - pint6 pint5 pint4 pint3 pint2 pint1 pint0 upint read/write initial value00000000 313 7593a?avr?02/06 at90usb64/128 24. analog comparator the analog comparator compares the input va lues on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on com- parator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 24-1 . the power reduction adc bit, pradc, in ?power reduction register 0 - prr0? on page 55 must be disabled by writing a logical zero to be able to use the adc input mux. figure 24-1. analog comparator block diagram (2) notes: 1. see table 24-2 on page 315 . 2. refer to figure 1-1 on page 3 and table 10-6 on page 81 for analog comparator pin placement. 24.0.1 adc control and stat us register b ? adcsrb ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 315 . 24.0.2 analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable acbg bandgap reference adc multiplexer output acme aden (1) bit 7 6543210 ?acme ? ? - adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value0 0000000 bit 76543210 acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 314 7593a?avr?02/06 at90usb64/128 when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog compar ator. this will reduce po wer consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. ot herwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference volt age replaces the positive input to the analog comparator. when this bit is clea red, ain0 is applied to the positive input of the analog compar- ator. see ?internal voltage reference? on page 63. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchron ized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers t he interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog com- parator interrupt is activated. when writ ten logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input ca pture function in timer/counter1 to be trig- gered by the analog comparator. the comparator outp ut is in this case directly connected to the input capture front-end logic, ma king the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and the input c apture function exists. to make the comparator trigger the timer/counter1 input capture interr upt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which compar ator events that trigger the an alog comparator interrupt. the different settings are shown in table 24-1 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr re gister. otherwise an interrupt can occur when the bits are changed. table 24-1. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. 315 7593a?avr?02/06 at90usb64/128 24.1 analog comparator multiplexed input it is possible to select any of the adc15..0 pins to replace t he negative input to the analog com- parator. the adc multiplexer is used to select this input, and conseq uently, the adc must be switched off to utilize this feature. if the a nalog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (aden in adcsra is zero), and mux2..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 24-2 . if acme is cleared or aden is set, ain1 is applied to the negative input to the ana- log comparator. 24.1.1 digital input disa ble register 1 ? didr1 ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digital input disable when this bit is written logic one, the digital inpu t buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit will always read as zero when th is bit is set. when an analog signal is applied to the ain1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. table 24-2. analog comparator mulitiplexed input acme aden mux2..0 analog comparator negative input 0xxxxain1 11xxxain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 bit 76543210 ? ? ? ? ? ? ain1d ain0d didr1 read/writerrrrrrr/wr/w initial value00000000 316 7593a?avr?02/06 at90usb64/128 25. analog to digital converter - adc 25.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 65 - 260 s conversion time ? up to 15 ksps at maximum resolution ? eight multiplexed single ended input channels ? seven differential input channels ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56 v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler the at90usb64/128 features a 10-bit successive approximation adc. the adc is connected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs constructed from the pins of port a. the single-e nded voltage inputs refer to 0v (gnd). the device also supports 16 differential voltage input combinations. two of the differential inputs (adc1, adc0 and adc3, adc2) are equipped wi th a programmable gain stage, providing amplification steps of 0 db (1x), 20 db (10x), or 46 db (200x) on the differential input voltage before the a/d conversion. seven differential analog input channels share a common negative terminal (adc1), while any other adc input can be selected as the positive input terminal. if 1x or 10x gain is used, 8-bit resolution can be expecte d. if 200x gain is used, 7-bit resolution can be expected. the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion . a block diagram of the adc is shown in figure 25-1 . the adc has a separate anal og supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 323 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pi n by a capacitor for be tter noise performance. 317 7593a?avr?02/06 at90usb64/128 figure 25-1. analog to digital converter block schematic 25.2 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags adhsm start 318 7593a?avr?02/06 at90usb64/128 the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differ ential gain are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. a selection of adc input pi ns can be selected as positive and negative inputs to the differential amplifier. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommende d to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then ad ch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be tr iggered when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 25.3 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered auto matically by various sour ces. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trig ger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if th e trigger signal is still set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger sign al during con- version, the edge will be ignored. note that an in terrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 319 7593a?avr?02/06 at90usb64/128 figure 25-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversion s can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independe ntly of how the conversion was started. 25.4 prescaling and conversion timing figure 25-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. alter- natively, setting the ad hsm bit in adcsrb allows an in creased adc clock frequency at the expense of higher power consumption. the adc module contains a prescaler, which generates an acceptab le adc clock frequency from any cpu frequency above 100 khz. the presca ling is set by the adps bits in adcsra. the prescaler starts counting from the moment th e adc is switched on by setting the aden bit adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset a den s tart 320 7593a?avr?02/06 at90usb64/128 in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by setti ng the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. see ?differential channels? on page 321 for details on different ial conversion timing. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc cl ock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of an first conversion. when a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the tr igger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately af ter the conversion com- pletes, while adsc remains high. for a summary of conversion times, see table 25-1 . figure 25-4. adc timing diagram, first conver sion (single conversion mode) figure 25-5. adc timing diagram, single conversion sign and msb of result lsb of result a dc clock a dsc sample & hold a dif a dch a dcl c ycle number a den 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and ref s update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result a dc clock a dsc a dif a dch a dcl c ycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and ref s update 321 7593a?avr?02/06 at90usb64/128 figure 25-6. adc timing diagram, auto triggered conversion figure 25-7. adc timing diagram, free running conversion 25.4.1 differential channels when using differential channels, certain aspe cts of the conversion need to be taken into consideration. differential conversions are synchronized to the internal clock ck adc2 equal to half the adc clock frequency. this synchroniza tion is done automatically by the adc interface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (i.e., all single conversions, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (1 3 adc clock cycles from the next prescaled clock cycle). a conversion initiated by the user when ck adc2 is high will take 14 adc table 25-1. adc conversion time condition first conversion normal conversion, single ended auto triggered convertion sample & hold (cycles from start of convertion) 14.5 1.5 2 conversion time (cycles) 25 13 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of resul t lsb of result a dc clock t rigger s ource a dif a dch a dcl c ycle number 12 one conversion next conversio n conversion complete prescaler reset a date prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result a dc clock a dsc a dif a dch a dcl c ycle number 12 one conversion next conversion 34 conversion complete sample & ho ld mux and refs update 322 7593a?avr?02/06 at90usb64/128 clock cycles due to the synchronization mechanis m. in free running mode, a new conversion is initiated immediately after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the fi rst) free running conversions will take 14 adc clock cycles. if differential channels are used and conversions are started by au to triggering, the adc must be switched off between conversions. when auto triggering is used, the adc prescaler is reset before the conversion is started. since the stage is dependent of a stable adc clock prior to the conversion, this conversion will not be valid. by disabling and then re-enabling t he adc between each conversion (writing aden in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see ?prescaling and conver- sion timing? on page 319 for timing details. the gain stage is optimized for a bandwidth of 4 kh z at all gain settings. higher frequencies may be subjected to non-linear amplification. an exte rnal low-pass filter shou ld be used if the input signal contains higher frequency components th an the gain stage bandwidth. note that the adc clock frequency is independent of the gain stage bandwidth limitation. e.g. the adc clock period may be 6 s, allowing a channel to be sampled at 12 ksps, regardless of the bandwidth of this channel. 25.5 changing channel or reference selection the muxn and refs1:0 bits in the admux regi ster are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensu re a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is writ ten to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differential channels. once a differential channel has been selected, the stage may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential chan- nel. alternatively, conversion results obt ained within this period should be discarded. the same settling time should be observed for th e first differential conversion after changing adc reference (by changing the refs1:0 bits in admux). 323 7593a?avr?02/06 at90usb64/128 the settling time and gain stage bandwidth is independent of the adhsm bit setting. 25.5.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the chan nel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selectio n. subsequent conversi ons will reflect the new channel selection. when switching to a differential gain channel, t he first conversion result may have a poor accu- racy due to the required settling time for the automatic offset cancellation circuitry. the user should preferably disregard the first conversion result. 25.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capaci tor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the ap plication, as they will be shorted to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 2.56v as reference selection. the first adc conversion re sult after switching reference voltage source may be inaccurate, and the user is advised to discard this result. if differential channels are used, the sele cted reference should not be closer to av cc than indi- cated in table 30-5 on page 407 . 25.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 324 7593a?avr?02/06 at90usb64/128 a. make sure that the adc is enabled and is not busy converti ng. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conver sion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conv ersion complete interrupt request will be genera ted when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will no t be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conver- sions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extended conversion to get a valid result. 25.6.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 25-8. an analog source applied to adcn is subjected to the pin capacitance and input leak age of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wit h an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpr edictable signal convolution. the user is advised to remove high frequency components with a lo w-pass filter before appl ying the signals as inputs to the adc. figure 25-8. analog input circuitry a dcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 325 7593a?avr?02/06 at90usb64/128 25.6.2 analog noise canceling techniques digital circuitry inside and outside the device gener ates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possi ble. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digi- tal tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 25-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 25-9. adc power connections 25.6.3 offset compensation schemes the gain stage has a built-in offset cancellation circuitry that null s the offset of differential mea- surements as much as possible. the remainin g offset in the analog path can be measured directly by selecting the same channel for both diff erential inputs. this offset residue can be then subtracted in software from the measurement results. using this kind of so ftware based offset correction, offset on any channel can be reduced below one lsb. 25.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: vcc gnd 100nf analog ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 53 54 55 56 57 58 59 60 6161 6262 6363 6464 1 51 nc (ad0) pa0 10 h 326 7593a?avr?02/06 at90usb64/128 ? offset: the deviation of the first transition (0 x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 25-10. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 25-11. gain error ? integral non-linearity (inl): afte r adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. o utput code v ref input voltage ideal adc actual ad c offset error o utput code v ref input voltage ideal adc actual ad c gain error 327 7593a?avr?02/06 at90usb64/128 figure 25-12. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actu al code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 25-13. differential non-linearity (dnl) ? quantization error: due to the quantization of th e input voltage into a finite number of codes, a range of input volt ages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. th is is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 25.7 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is: o utput code v ref input voltage ideal adc actual ad c inl o utput code 0x3ff 0x000 0 v ref input voltag e dnl 1 lsb 328 7593a?avr?02/06 at90usb64/128 where v in is the voltage on the se lected input pin and v ref the selected voltage reference (see table 25-3 on page 330 and table 25-4 on page 330 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) th rough 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the result , it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, th e result is negative, and if this bit is zero, the result is posi- tive. figure 25-14 shows the decoding of the differential input range. table 82 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a reference voltage of v ref . figure 25-14. differential measurement range adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? () gain 512 ?? v ref ------------------------------------------------------------------------ = 0 output code 0x1ff 0x000 v ref differential inp ut voltage (volts) 0x3ff 0x200 - v ref 329 7593a?avr?02/06 at90usb64/128 example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2. 56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. 25.8 adc register description 25.8.1 adc multiplexer selection register ? admux ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 25-3 . if these bits are changed during a conversion, the change will not go in effect until this co nversion is complete table 25-2. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 bit 76543210 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 330 7593a?avr?02/06 at90usb64/128 (adif in adcsra is set). the internal voltage re ference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherw ise, the result is right adjusted. changing the adlar bit will affect t he adc data register immediately, regardless of any ongoing conver- sions. for a complete description of this bit, see ?the adc data register ? adcl and adch? on page 332 . ? bits 4:0 ? mux4:0: analog channel selection bits the value of these bits selects which combinatio n of analog inputs are connected to the adc. these bits also select the gain for the differential channels. see table 25-4 for details. if these bits are changed during a conversion, the change wil l not go in effect until this conversion is complete (adif in adcsra is set). table 25-3. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal vref turned off 01av cc with external capacitor on aref pin 10reserved 1 1 internal 2.56v voltage reference with external capacitor on aref pin table 25-4. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 331 7593a?avr?02/06 at90usb64/128 25.8.2 adc control and stat us register a ? adcsra ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writi ng it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, 01000 n/a (adc0 / adc0 / 10x) 01001 adc1 adc0 10x 01010 (adc0 / adc0 / 200x) 01011 adc1 adc0 200x 01100 (reserved - adc2 / adc2 / 10x) 01101 adc3 adc2 10x 01110 (adc2 / adc2 / 200x) 01111 adc3 adc2 200x 10000 adc0 adc1 1x 10001 (adc1 / adc1 / 1x) 10010 adc2 adc1 1x 10011 adc3 adc1 1x 10100 adc4 adc1 1x 10101 adc5 adc1 1x 10110 adc6 adc1 1x 10111 adc7 adc1 1x 11000 adc0 adc2 1x 11001 adc1 adc2 1x 11010 (adc2 / adc2 / 1x) 11011 adc3 adc2 1x 11100 adc4 adc2 1x 11101 adc5 adc2 1x 11110 1.1v (v band gap ) n/a 11111 0v (gnd) table 25-4. input channel and gain selections (continued) mux4..0 single ended input positive differential input negative differential input gain bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 332 7593a?avr?02/06 at90usb64/128 will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the co nversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing th e corresponding interrupt handling vector. alter- natively, adif is cleared by writ ing a logical one to the flag. beware that if doing a read-modify- write on adcsra, a pending interrupt can be dis abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor betwe en the xtal frequency and the input clock to the adc. 25.8.3 the adc data register ? adcl and adch 25.8.3.1 adlar = 0 table 25-5. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 bit 151413121110 9 8 ? ? ? ? ? ? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 333 7593a?avr?02/06 at90usb64/128 25.8.3.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. if differential channels are used, the result is presented in two?s complement form. when adcl is read, the adc data register is not updated until adch is read. consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bi t for differential input channels) is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result fr om the conversion, as detailed in ?adc conversion result? on page 327 . 25.8.4 adc control and stat us register b ? adcsrb ? bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. this mode enables higher conversion rate at the expense of higher power consumption. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selected inte rrupt flag. note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. s witching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set . bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ????? adcl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 76543210 adhsm acme ? ? ? adts2 adts1 adts0 adcsrb read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 25-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 334 7593a?avr?02/06 at90usb64/128 25.8.5 digital input disa ble register 0 ? didr0 ? bit 7:0 ? adc7d..adc0d: ad c7:0 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin regist er bit will always read as zero w hen this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event table 25-6. adc auto trigger source selections adts2 adts1 adts0 trigger source bit 76543210 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 335 7593a?avr?02/06 at90usb64/128 26. jtag interface and on-chip debug system 26.0.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ?program counter ? eeprom and flash memories ? extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on single address or address range ? programming of flash, eeprom , fuses, and lock bits th rough the jtag interface ? on-chip debugging supported by avr studio ? 26.1 overview the avr ieee std. 1149.1 compliant jtag interface can be used for ? testing pcbs by using the jtag boundary-scan capability ? programming the non-volatile memories, fuses and lock bits ? on-chip debugging a brief description is given in the following se ctions. detailed descriptions for programming via the jtag interface, and using the boundary-scan chain can be found in the sections ?program- ming via the jtag interface? on page 387 and ?ieee 1149.1 (jtag) boun dary-scan? on page 341 , respectively. the on-chip debug support is considered being private jtag instructions, and distributed within atmel and to selected third pa rty vendors only. figure 26-1 shows a block diagram of the jtag interface and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the be havior of a data register. the id-register, bypass register , and the boundary-scan chain are the data registers used for board-level testing. the jtag programming in terface (actually consisting of several physical and virtual data registers) is used for serial pr ogramming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. 26.2 test access port ? tap the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: ? tms: test mode select. this pin is used for navigating through the tap-controller state machine. ? tck: test clock. jtag operation is synchronous to tck. 336 7593a?avr?02/06 at90usb64/128 ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo: test data out. serial output data fr om instruction register or data register. the ieee std. 1149.1 also specif ies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is unprogrammed, these four tap pins are normal port pins, and the tap controller is in reset. when programmed, t he input tap signals are internally pulled high and the jtag is enabled for boundary-scan and pr ogramming. the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is moni- tored by the debugger to be able to detect exte rnal reset sources. the debugger can also pull the reset pin low to reset the whole system, assumi ng only open collectors on the reset line are used in the application. figure 26-1. block diagram tap controller t di t do t ck t ms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pc instruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0 i/o port n boundary scan chain analog inputs control & clock line s device boundary 337 7593a?avr?02/06 at90usb64/128 figure 26-2. tap controller state diagram 26.3 tap controller the tap controller is a 16-state finite state mach ine that controls the operation of the boundary- scan circuitry, jtag programmi ng circuitry, or on-chip debug system. the state transitions depicted in figure 26-2 depend on the signal present on tm s (shown adjacent to each state transition) at the time of the ri sing edge at tck. the initial stat e after a power-on reset is test- logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a ty pical scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? sh ift-ir state. while in this state, shift the four bits of the jtag instructions into the jt ag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instructi on is shifted in when this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a par ticular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 338 7593a?avr?02/06 at90usb64/128 ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-i r state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr state. while in this state, upload the selected data register (selected by the present jtag instruction in th e jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latc hing takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states ar e only used for navigating the state machine. as shown in the state diagram, the run-tes t/idle state need not be entered between selecting jtag instruction and using data registers, and some jtag inst ructions may select certain functions to be performed in the run-test/idl e, making it unsuitable as an idle state. note: independent of the initial state of the tap c ontroller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specif ication, refer to the literature listed in ?bibliography? on page 340 . 26.4 using the boundary-scan chain a complete description of the boundary-sc an capabilities are gi ven in the section ?ieee 1149.1 (jtag) boundary-scan? on page 341 . 26.5 using the on-c hip debug system as shown in figure 26-1 , the hardware support for on-chip debugging consists mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? break point unit. ? communication interface between the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: ? 4 single program memory break points. ? 3 single program memory break point + 1 single data memory break point. ? 2 single program memory break points + 2 single data memory break points. ? 2 single program memory break points + 1 program memory break point with mask (?range break point?). 339 7593a?avr?02/06 at90usb64/128 ? 2 single program memory break points + 1 data memory break point with mask (?range break point?). a debugger, like the avr studio, may however use one or more of these resources for its inter- nal purpose, leaving less flexibility to the end-user. a list of the on-chip debug specific jtag instructions is given in ?on-chip debug specific jtag instructions? on page 339 . the jtagen fuse must be programmed to enable the jtag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chip debug system would have provided a back-door into a secu red device. the avr studio enables the user to fully contro l execution of programs on an avr device with on-chip debug capability, avr in- circuit emulator, or the built-in avr instruction set simulator. avr studio ? supports source level execution of assembly programs assembled with atmel cor- poration?s avr assembler and c programs compiled with third party vendors? compilers. avr studio runs under microsoft ? windows ? 95/98/2000 and microsoft windows nt ? . for a full description of the avr studio, please re fer to the avr studio user guide. only high- lights are presented in this document. all necessary execution commands are available in avr studio, both on source level and on disassembly level. the user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the st atement is reached, stop the execution, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instruction) and up to two data memory break po ints, alternatively combined as a mask (range) break point. 26.6 on-chip debug specific jtag instructions the on-chip debug support is considered being priv ate jtag instructions, and distributed within atmel and to selected third pa rty vendors only. instruction opcodes are listed for reference. 26.6.1 private0; 0x8 private jtag instruction for accessing on-chip debug system. 26.6.2 private1; 0x9 private jtag instruction for accessing on-chip debug system. 26.6.3 private2; 0xa private jtag instruction for accessing on-chip debug system. 26.6.4 private3; 0xb private jtag instruction for accessing on-chip debug system. 340 7593a?avr?02/06 at90usb64/128 26.7 on-chip debug related register in i/o memory 26.7.1 on-chip debug register ? ocdr the ocdr register provides a co mmunication channel from the running pr ogram in the micro- controller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an inte rnal flag; i/o debug re gister dirty ? idrd ? is set to indicate to the debugger that the register has been writ ten. when the cpu reads the ocdr register the 7 lsb will be from the ocdr regi ster, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared wi th a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other case s, the standard i/o location is accessed. refer to the debugger documentation for furt her information on how to use this register. 26.8 using the jtag programming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag program- ming (in addition to power pins). it is not requi red to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mc ucr register must be cleared to enable the jtag test access port. the jtag programmi ng capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in parallel programming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag instructions are given in the section ?programming via the jtag interface? on page 387 . 26.9 bibliography for more information about general boundary-scan, the following literature can be consulted: ? ieee: ieee std. 1149.1-1990. ieee standard test access port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testable logic circuits, addison-wesley, 1992. bit 7 6543210 msb/idrd lsb ocdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 341 7593a?avr?02/06 at90usb64/128 27. ieee 1149.1 (jtag) boundary-scan 27.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? full scan of all port functions as well as analog circuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset the avr 27.2 system overview the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe t he input values received from other devices. the controller compares the received data with the ex pected result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode , bypass, sample/pre- load, and extest, as well as the avr specif ic public jtag instruction avr_reset can be used for testing the print ed circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the device may be deter- mined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. en tering reset, the outputs of any port pin will instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset instruction with appropriate setti ng of the reset data register. the extest instruction is used for sampling exte rnal pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be prog rammed and the jtd bit in th e i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. 27.3 data registers the data registers relevant for boundary-scan operations are: ? bypass register ? device identific ation register ? reset register ? boundary-scan chain 342 7593a?avr?02/06 at90usb64/128 27.3.1 bypass register the bypass register consists of a single shift register stage. when the bypass register is selected as path between tdi and tdo, the regist er is reset to 0 when leaving the capture-dr controller state. the bypass regi ster can be used to shorten the scan chain on a system when the other devices are to be tested. 27.3.2 device identification register figure 27-1 shows the structure of the de vice identification register. figure 27-1. the format of the device identification register 27.3.2.1 version version is a 4-bit number identifying the revision of the component. the jtag version number follows the revision of the device. revision a is 0x0, revision b is 0x1 and so on. 27.3.2.2 part number the part number is a 16-bit code identifying the component. the jtag part number for at90usb64/128 is listed in table 27-1 . 27.3.2.3 manufacturer id the manufacturer id is a 11-bit code identify ing the manufacturer. the jtag manufacturer id for atmel is listed in table 27-2 . 27.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also re place the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse set- tings for the clock options, the part will remain reset for a reset time-out period (refer to ?clock sources? on page 39 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 27-2 . msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit table 27-1. avr jtag part number part number jtag part number (hex) avr usb 0x9782 table 27-2. manufacturer id manufacturer jtag manufactor id (hex) atmel 0x01f 343 7593a?avr?02/06 at90usb64/128 figure 27-2. reset register 27.3.4 boundary-scan chain the boundary-scan chain has the capability of driv ing and observing the lo gic levels on the dig- ital i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 345 for a complete description. 27.4 boundary-scan specifi c jtag instructions the instruction register is 4-bit wide, suppor ting up to 16 instructions . listed below are the jtag instructions useful for boundary-scan operat ion. note that the opti onal highz instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the avr_reset inst ruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. 27.4.1 extest; 0x0 mandatory jtag instruction for selecting the bo undary-scan chain as data register for testing circuitry external to the avr package. for port-pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog ci rcuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. the con- tents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir- register is loaded with the extest instruction. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the internal scan chain is shifted by the tck input. ? update-dr: data from the scan chain is applied to output pins. 27.4.2 idcode; 0x1 optional jtag instruction select ing the 32 bit id-register as da ta register. the id-register consists of a version number, a device number and the manufacturer code chosen by jedec. this is the default inst ruction after power-up. dq from tdi clockdr avr_reset to tdo from other internal and external reset sources internal reset 344 7593a?avr?02/06 at90usb64/128 the active states are: ? capture-dr: data in the idcode register is sampled into the boundary-scan chain. ? shift-dr: the idcode scan chai n is shifted by the tck input. 27.4.3 sample_preload; 0x2 mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecti ng the system operation. howeve r, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the boundary-scan chain is shifted by the tck input. ? update-dr: data from the boundary-scan chai n is applied to the output latches. however, the output latches are not connected to the pins. 27.4.4 avr_reset; 0xc the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset will be active as lo ng as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 27.4.5 bypass; 0xf mandatory jtag instructio n selecting the bypass register for data register. the active states are: ? capture-dr: loads a logic ?0? into the bypass register. ? shift-dr: the bypass register ce ll between tdi and tdo is shifted. 27.5 boundary-scan related register in i/o memory 27.5.1 mcu control register ? mcucr the mcu control register contains co ntrol bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is enabl ed if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in or der to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to th e desired value twice within four cycles to change its value. note that this bit must not be altered when using the on-chip debug system. bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 345 7593a?avr?02/06 at90usb64/128 27.5.2 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is rese t by a power-on reset, or by writing a logic zero to the flag. 27.6 boundary-scan chain the boundary-scan chain has the capability of drivin g and observing the logi c levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connection. 27.6.1 scanning the digital port pins figure 27-3 shows the boundary-scan cell for a bi-dir ectional port pin. the pull-up function is disabled during boundary-scan when the jtag ic contains extest or sample_preload. the cell consists of a bi-directional pin cell th at combines the three signals output control - ocxn, output data - odxn, and in put data - idxn, into only a tw o-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not include d in the figures in the datasheet. figure 27-4 shows a simple digital port pin as described in the section ?i/o-ports? on page 73 . the boundary-scan details from figure 27-3 replaces the dashed box in figure 27-4 . when no alternate port function is present, the in put data - id - corresponds to the pinxn regis- ter value (but id has no synchroni zer), output data corresponds to the port register, output control corresponds to the data direction - dd register, and th e pull-up enable - puexn - cor- responds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 27-4 to make the scan chain read the actual pin value. for analog f unction, there is a direct connection from the external pin to the analog circuit. there is no scan chain on the interfac e between the digital and the analog circuitry, but some digital control signal to analog circuitry are turned off to avoid driv- ing contention on the pads. when jtag ir contains extest or sample_preload the clock is not sent out on the port pins even if the ckout fuse is programmed. even though the cloc k is output when the jtag ir contains sample_preload, the clock is not sampled by the boundary scan. bit 76543210 ? ? ?jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description 346 7593a?avr?02/06 at90usb64/128 figure 27-3. boundary-scan cell for bi-directional port pin with pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 port pin (pxn) vcc extest to next cell shiftdr output control (oc) output data (od) input data (id) from last cell updatedr clockdr ff1 ld1 ld0 ff0 0 1 pull-up enable (pue) 347 7593a?avr?02/06 at90usb64/128 figure 27-4. general port pin schematic diagram 27.6.2 scanning the reset pin the reset pin accepts 5v active low logic fo r standard reset operation, and 12v active high logic for high voltage parallel programming. an observe-only cell as shown in figure 27-5 is inserted for the 5v reset signal. figure 27-5. observe-only cell clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn 0 1 dq from previous cell clockdr shiftdr to next cell from system pin to system logic ff1 348 7593a?avr?02/06 at90usb64/128 27.7 at90usb64/128 boundary-scan order table 27-3 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as poss ible. therefore, the bits of port a and port fis scanned in the opposite bit order of the other por ts. exceptions from the rules are the scan chains for the analog circuits, which constitute th e most significant bits of the scan chain regard- less of which physical pin they are connected to. in figure 27-3 , pxn. data corresponds to ff0, pxn. control corresponds to ff1, pxn. bit 4, 5, 6 and 7 of port f is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. the usb pads are not included in the boundary-scan. table 27-3. at90usb64/128 boundary-scan order bit number signal name module 88 pe6.data port e 87 pe6.control 86 pe7.data 85 pe7.control 84 pe3.data 83 pe3.control 82 pb0.data port b 81 pb0.control 80 pb1.data 79 pb1.control 78 pb2.data 77 pb2.control 76 pb3.data 75 pb3.control 74 pb4.data 73 pb4.control 72 pb5.data 71 pb5.control 70 pb6.data 69 pb6.control 68 pb7.data 67 pb7.control 66 pe4.data porte 65 pe4.control 64 pe5.data 63 pe5.control 349 7593a?avr?02/06 at90usb64/128 62 rstt reset logic (observe only) 61 pd0.data port d 60 pd0.control 59 pd1.data 58 pd1.control 57 pd2.data 56 pd2.control 55 pd3.data 54 pd3.control 53 pd4.data 52 pd4.control 51 pd5.data 50 pd5.control 49 pd6.data 48 pd6.control 47 pd7.data 46 pd7.control 45 pe0.data port e 44 pe0.control 43 pe1.data 42 pe1.control table 27-3. at90usb64/128 boundary-scan order (continued) bit number signal name module 350 7593a?avr?02/06 at90usb64/128 41 pc0.data port c 40 pc0.control 39 pc1.data 38 pc1.control 37 pc2.data 36 pc2.control 35 pc3.data 34 pc3.control 33 pc4.data 32 pc4.control 31 pc5.data 30 pc5.control 29 pc6.data 28 pc6.control 27 pc7.data 26 pc7.control 25 pe2.data port e 24 pe2.control 23 pa7.data port a 22 pa7.control 21 pa6.data 20 pa6.control 19 pa5.data 18 pa5.control 17 pa4.data 16 pa4.control 15 pa3.data 14 pa3.control 13 pa2.data 12 pa2.control 11 pa1.data 10 pa1.control 9pa0.data 8 pa0.control table 27-3. at90usb64/128 boundary-scan order (continued) bit number signal name module 351 7593a?avr?02/06 at90usb64/128 27.8 boundary-scan description language files boundary-scan description language (b sdl) files describe boundary-scan capable devices in a standard format used by automated test-generati on software. the order and function of bits in the boundary-scan data register are included in th is description. bsdl files are available for at90usb64/128. 7pf3.data port f 6 pf3.control 5pf2.data 4 pf2.control 3pf1.data 2 pf1.control 1pf0.data 0 pf0.control table 27-3. at90usb64/128 boundary-scan order (continued) bit number signal name module 352 7593a?avr?02/06 at90usb64/128 28. boot loader supp ort ? read-while-wri te self-programming the boot loader support provides a real read- while-write self-programming mechanism for downloading and uploading program code by the m cu itself. this feature a llows flexible applica- tion software updates controlled by the mcu us ing a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program mem- ory. the program code within the boot loader sect ion has the capability to write into the entire flash, including the boot loader memory. the boot loader can t hus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and t he boot loader has two separate sets of boot lock bits which can be set indepen dently. this gives the user a uniq ue flexibility to select differ- ent levels of protection. general information on spm and elpm is provided in see ?avr cpu core? on page 9. 28.1 boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modi fy-write support note: 1. a page is a section in the flash consisting of several bytes (see table 29-11 on page 373 ) used during programming. the page organization does not affect normal operation. 28.2 application and boot loader flash sections the flash memory is organized in two main se ctions, the application section and the boot loader section (see figure 28-2 ). the size of the different se ctions is configured by the bootsz fuses as shown in table 28-8 on page 366 and figure 28-2 . these two sections can have different level of protection since they have different sets of lock bits. 28.2.1 application section the application section is the section of the flas h that is used for storing the application code. the protection level for the application section c an be selected by the application boot lock bits (boot lock bits 0), see table 28-2 on page 356 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 28.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entir e flash, including the bls itself. the protection level for the boot loa der section can be selected by the boot loader lock bits (boot lock bits 1), see table 28-3 on page 356 . 28.3 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two 353 7593a?avr?02/06 at90usb64/128 sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-whi le-write (rww) secti on and the no read-while- write (nrww) section. the limit between the rww- and nrww sections is given in table 28- 1 and figure 28-1 on page 354 . the main difference between the two sections is: ? when erasing or writing a page located insi de the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located insi de the rww section dur- ing a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or writ ten), not which section that actually is being read during a boot loader software update. 28.3.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is lo cated inside the rww section (i.e., by load program memory, call, or jump instructions or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the inte rrupts should either be disabled or moved to the boot loader section. the boot loader section is always locat ed in the nrww section. the rww section busy bit (rwwsb) in the store pr ogram memory control and status register (spmcsr) will be read as logica l one as long as the rww sectio n is blocked for reading. after a programming is completed, the rwwsb mu st be cleared by software before reading code located in the rww section. see ?store program memory control and status register ? spmcsr? on page 358. for details on how to clear rwwsb. 28.3.2 nrww ? no read -while-write section the code located in the nrww section can be re ad when the boot loader software is updating a page in the rww section. when the boot l oader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 28-1. read-while-write features which section does the z- pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 354 7593a?avr?02/06 at90usb64/128 figure 28-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 355 7593a?avr?02/06 at90usb64/128 figure 28-2. memory sections note: 1. the parameters in the figure above are given in table 28-8 on page 366 . 28.4 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash sect ion from a software update by the mcu. ? to protect only the application flash se ction from a software update by the mcu. ? allow software update in the entire flash. see table 28-2 and table 28-3 for further details. the boot lock bits can be set by software and in serial or in parallel programming mode. they can only be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. sim ilarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by (e )lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 356 7593a?avr?02/06 at90usb64/128 note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 28.5 entering the boot loader program the bootloader can be executed wi th three different conditions: 28.5.1 regular applic ation conditions. a jump or call from the application program. th is may be initiated by a trigger such as a com- mand received via usart, spi or usb. 28.5.2 boot reset fuse the boot reset fuse (bootrst) can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in th is case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itse lf. this means that once the boot reset fuse table 28-2. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 28-3. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and (e)lpm executing from t he application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 357 7593a?avr?02/06 at90usb64/128 is programmed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed 28.5.3 external ha rdware conditions the hardware boot enable fuse (hwbe) can be programmed (see table 28-5 ) so that upon special hardware conditions under reset, the bootloader execution is forced after reset. note: 1. ?1? means unprogrammed, ?0? means programmed when the hwbe fuse is enable the ale/hwb pin is configured as input during reset and sam- pled during reset rising edge. when ale/hwb pin is ?0? during reset rising edge, the reset vector will be set as the boot loader re set address and the bo ot loader will be exec uted (see figures 28-3). table 28-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 28-8 on page 366 ) table 28-5. hardware boot enable fuse (1) hwbe reset address 1ale/hwb pin can not be used to force boot loader execution after reset 0ale/hwb pin is used during reset to force bootloader execution after reset 358 7593a?avr?02/06 at90usb64/128 figure 28-3. boot process description 28.5.4 store program memory control and status register ? spmcsr the store program memory control and status regi ster contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready in terrupt will be ex ecuted as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one ) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alter natively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within three clock cycles will read a byte from the signatu re row into the dest ination register. see ?reading the signature row from software? on page 363 for details. an spm inst ruction within four cycles hwbe bootrst ? ext. hardware conditions ? reset vector = application reset reset vector =boot lhoader reset ? reset ale/hwb t shrh t hhrh bit 7 6 5 4 3 2 1 0 spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 359 7593a?avr?02/06 at90usb64/128 after sigrd and spmen are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by ha rdware). to re-enable the rww section, the user software must wait until the programming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww secti on. the rww section cannot be re-enabled while the flash is busy with a page erase or a page wr ite (spmen is set). if the rwwsre bit is writ- ten while the flash is being l oaded, the flash load operation w ill abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z- pointer are ignored. the blbset bit will autom atically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an (e)lpm instructio n within three cycles after blbset and spmen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z-po inter) into the destination register. see ?reading the fuse and lock bits from software? on page 363 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon comp letion of a page write, or if no spm instruction is exec uted within four clock cycles. the cpu is halted during the entire page write operat ion if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pg ers bit will auto-clear upon co mpletion of a page erase, or if no spm instruction is executed within four cl ock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next fo ur clock cycles. if written to one together with either rwwsre, blbset, pgwrt? or pgers, t he following spm instruction will have a spe- cial meaning, see description abo ve. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto- clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during pa ge erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 360 7593a?avr?02/06 at90usb64/128 note: only one spm instruction should be active at any time. 28.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer consists of the z-registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. note that the rampz register is only implemented when the pro- gram space is larger than 64k bytes. since the flash is organized in pages (see table 29-11 on page 373 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 28-4 . note that the page erase and page write operations are addressed independently. therefore it is of major importance th at the boot loader software addresses the same page in both the page eras e and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the (e)lpm instruction use the z-pointer to st ore the address. since this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointer is used. figure 28-4. addressing the flash during spm (1) bit 2322212019181716 15 14 13 12 11 10 9 8 rampz rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 program memory 0 1 23 z - pointer bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter 361 7593a?avr?02/06 at90usb64/128 note: 1. the different variables used in figure 28-4 are listed in table 28-10 on page 367 . 28.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled ei ther before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, th e rest of the page must be stored (for example in the temporary page buffer) before the erase, an d then be rewritten. when using alternative 1, the boot loader provides an effective read-mod ify-write feature which a llows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read t he old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 364 for an assembly code example. 28.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycl es after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 28.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the addres s in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. no te that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is wr itten in the middle of an spm page load operation, all data loaded will be lost. 28.7.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycl es after writing spmcsr. the data in r1 and r0 is ignored. 362 7593a?avr?02/06 at90usb64/128 the page address must be written to pcpage. ot her bits in the z-point er must be written to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 28.7.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant in terrupt when the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in softwar e. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an in terrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 69 . 28.7.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental writ e to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 28.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself mu st prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be se t as long as the rww section is busy. during self-programming the inte rrupt vector table should be moved to the bls as described in ?interrupts? on page 69 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 364 for an example. 28.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the de sired data to r0, write ?x0001001? to spmcsr and execute spm within four cloc k cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that ma y prevent the application and boot loader section from any soft- ware update by the mcu. see table 28-2 and table 28-3 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t ca re during this operation, but for futu re compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when pro- gramming the lock bits the entire flash can be read during the operation. 28.7.8 eeprom write prevents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during t he eeprom write operation. it bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 363 7593a?avr?02/06 at90usb64/128 is recommended that the user checks the st atus bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 28.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bi ts from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an (e)lpm instruction is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bi ts will be loaded in the destination regi ster. the blbset and spmen bits will auto-clear upon comple tion of reading the lock bits or if no (e)l pm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, (e)lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an (e)lpm inst ruction is executed within three cycles after the blbset and spmen bits are set in the spmc sr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 29-5 on page 370 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, l oad 0x0003 in the z-pointer. when an (e)lpm instruction is executed within three cycles a fter the blbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be loaded in the destinati on register as shown below. refer to table 29-4 on page 370 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x 0002 in the z-pointer. when an (e)lpm instruc- tion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the exten ded fuse byte (efb) will be loaded in the destination r egister as shown below. refer to table 29-3 on page 369 for detailed description an d mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 28.7.10 reading the signa ture row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 28-6 on page 364 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycl es after the sigrd and spmen bits are set in spmcsr, the signature byte valu e will be loaded in the destin ation register. the sigrd and spmen bits will auto-clear upon completion of re ading the signature row lo ck bits or if no lpm bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 7654 3210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 7654 3210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 7654 3210 rd ? ? ? ? ? efb2 efb1 efb0 364 7593a?avr?02/06 at90usb64/128 instruction is executed within three cpu cycles. when sigrd and spmen are cl eared, lpm will work as described in the instruction set manual. note: all other addresses are reserved for future use. 28.7.11 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient po wer supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the po wer supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 28.7.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 28-7 shows the typical pro- gramming time for flash accesses from the cpu. 28.7.13 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space table 28-6. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 0x0001 table 28-7. spm programming time symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 365 7593a?avr?02/06 at90usb64/128 ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 368 7593a?avr?02/06 at90usb64/128 29. memory programming 29.1 program and data memory lock bits the at90usb64/128 provides six lock bits whic h can be left unprogrammed (?1?) or can be pro- grammed (?0?) to obtain the ad ditional features listed in table 29-2 . the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed table 29-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 29-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in para llel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 369 7593a?avr?02/06 at90usb64/128 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 29.2 fuse bits the at90usb64/128 has four fuse bytes. table 29-3 - table 29-5 describe briefly the function- ality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. note: 1. see table 8-2 on page 61 for bodlevel fuse decoding. blb1 mode blb12 blb11 111 no restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and (e)lpm executing from t he application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 29-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 29-3. extended fuse byte fuse low byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 hwbe 3 hardware boot enable 0 (programmed) bodlevel2 (1) 2 brown-out detector tri gger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector tri gger level 1 (unprogrammed) bodlevel0 (1) 0 brown-out detector tri gger level 1 (unprogrammed) 370 7593a?avr?02/06 at90usb64/128 note: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1..0 results in maximum boot size. see table 28-8 on page 366 for details. 3. see ?watchdog timer control register - wdtcsr? on page 66 for details. 4. never ship a product with the ocden fuse programmed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse enables some parts of the clock system to be running in all sleep modes. this may increase the power consumption. note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 8-1 on page 59 for details. 2. the default settin g of cksel3..0 results in inter nal rc oscillator @ 8 mhz. see table 6-1 on page 39 for details. 3. the ckout fuse allow the system cl ock to be output on portc7. see ?clock output buffer? on page 47 for details. 4. see ?system clock prescaler? on page 47 for details. the status of the fuse bits is not affected by ch ip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. table 29-4. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bootsz1 2 select boot size (see table 29-6 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 29-6 for details) 0 (programmed) (2) bootrst 0 select reset vector 1 (unprogrammed) table 29-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 371 7593a?avr?02/06 at90usb64/128 29.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. 29.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. at90usb64/128 signature bytes: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x97 (indicates 128kb flash memory). 3. 0x002: 0x82 (indicates at90usbxxxdevice). 29.4 calibration byte the at90usb64/128 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in the signature address space. during reset, this byte is automatically written into the osccal regist er to ensure correct frequency of the calibrated rc oscillator. 29.5 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90usb64/128. pulses are assumed to be at least 250 ns unless otherwise noted. 29.5.1 signal names in this section, some pins of the at90usb64/128 are referenced by signal names describing their functionality during pa rallel programming, see figure 29-1 and table 29-6 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the ac tion executed when the xtal1 pi n is given a positive pulse. the bit coding is shown in table 29-9 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 29-10 . 372 7593a?avr?02/06 at90usb64/128 figure 29-1. parallel programming (1) note: 1. unused pins should be left floating. table 29-6. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). wr pd3 i write pulse (active low). bs1 pd4 i byte select 1. xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2. data pb7-0 i/o bi-directional data bus (output when oe is low). table 29-7. bs2 and bs1 encoding bs2 bs1 flash / eeprom address flash data loading / reading fuse programming reading fuse and lock bits 0 0 low byte low byte low byte fuse low byte 0 1 high byte high byte high byte lockbits 10 extended high byte reserved extended byte extended fuse byte 1 1 reserved reserved reserved fuse high byte vcc +5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 dat a reset pd7 +12 v bs1 xa0 xa1 oe r dy/bsy pagel pa0 wr bs2 avcc +5v 373 7593a?avr?02/06 at90usb64/128 , table 29-8. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 29-9. xa1 and xa0 enoding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs2 and bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 29-10. command byte bit encoding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 29-11. no. of words in a page and no. of pages in the flash flash size page size pcword no. of pages pcpage pcmsb 128k words (256k bytes) 128 words pc[6:0] 1024 pc[16:7] 16 374 7593a?avr?02/06 at90usb64/128 29.6 parallel programming 29.6.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 29-8 on page 373 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. 29.6.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) a nd flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 29.6.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during ch ip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive puls e. this loads the command. 5. give wr a negative pulse. this st arts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. table 29-12. no. of words in a page and no. of pages in the eeprom eeprom size page size pcword no. of pages pcpage eeamsb 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11 375 7593a?avr?02/06 at90usb64/128 29.6.4 programming the flash the flash is organized in pages, see table 29-11 on page 373 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive puls e. this loads the command. b. load address low byte (address bits 7..0) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?00?. this selects the address low byte. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 29-3 for signal waveforms) f. repeat b through e until the entire buffer is f illed or until all data withi n the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash . this is illustrated in figure 29-2 on page 376 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte (address bits15..8) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?01?. this selects the address high byte. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. load address extended high byte (address bits 23..16) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?10?. this selects the address extended high byte. 376 7593a?avr?02/06 at90usb64/128 3. set data = address extended high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. i. program page 1. set bs2, bs1 to ?00? 2. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 3. wait until rdy/bsy goes high (see figure 29-3 for signal waveforms). j. repeat b through i until the entire flash is programmed or until all data has been programmed. k. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. figure 29-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 29-11 on page 373 . program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 377 7593a?avr?02/06 at90usb64/128 figure 29-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. 29.6.5 programming the eeprom the eeprom is organized in pages, see table 29-12 on page 374 . when programming the eeprom, the program data is latche d into a page buffer. this allo ws one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 375 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs2, bs1 to ?00?. 2. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 29-4 for signal waveforms). rdy/bsy wr oe r eset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdeg f addr. ext.h h i 378 7593a?avr?02/06 at90usb64/128 figure 29-4. programming the eeprom waveforms 29.6.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 375 for details on command and address loading): 1. a: load command ?0000 0010?. 2. h: load address extended byte (0x00- 0xff). 3. g: load address high byte (0x00 - 0xff). 4. b: load address low byte (0x00 - 0xff). 5. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 6. set bs to ?1?. the flash word high byte can now be read at data. 7. set oe to ?1?. 29.6.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 375 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0 ?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 29.6.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 375 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. rdy/bsy wr oe r eset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 379 7593a?avr?02/06 at90usb64/128 29.6.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 375 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?01?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2, bs1 to ?00?. th is selects low data byte. 29.6.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 375 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs2, bs1 to ?10?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2, bs1 to ?00?. th is selects low data byte. figure 29-5. programming the fuses waveforms 29.6.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 375 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 380 7593a?avr?02/06 at90usb64/128 29.6.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 375 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, and bs2, bs1 to ?00?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, and bs2, bs1 to ?11?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, and bs2, bs1 to ?10?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, and bs2, bs1 to ?01?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 29-6. mapping between bs1, bs2 and the fuse and lock bits during read 29.6.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 375 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 29.6.14 reading the calibration byte the algorithm for reading the calibrati on byte is as follows (refer to ?programming the flash? on page 375 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 381 7593a?avr?02/06 at90usb64/128 29.6.15 parallel programming characteristics figure 29-7. parallel programming timing, including some general timing requirements figure 29-8. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 29-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. figure 29-9. parallel programming timing, reading sequence (within the same page) with timing requirements (1) data & contol ( data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 p agel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) x tal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 382 7593a?avr?02/06 at90usb64/128 note: 1. the timing requirements shown in figure 29-7 (i.e., t dvxh , t xhxl , and t xldx ) also apply to read- ing operation. notes: 1. t wlrh is valid for the write flash, write eeprom , write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 29.7 serial downloading both the flash and eeprom memo ry arrays can be programmed using a serial programming bus while reset is pulled to gnd. the serial programming interface consists of pins sck, pdi (input) and pdo (output). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 29-14 on page 383 , the pin mapping for serial programming is listed. not all packages use the spi pins dedicated for the internal serial peripheral interface - spi. table 29-13. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs2/1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 383 7593a?avr?02/06 at90usb64/128 29.8 serial programming pin mapping figure 29-10. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 1.8 - 5.5v when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 29.8.1 serial programming algorithm when writing serial data to the at90usb64/12 8, data is clocked on the rising edge of sck. when reading data from the at90usb64/128, dat a is clocked on the falling edge of sck. see figure 29-11 for timing details. to program and verify the at90usb64/128 in t he serial programming mode, the following sequence is recommended (see four byte instruction formats in table 29-16 ): table 29-14. pin mapping serial programming symbol pins (tqfp-100) pins (tqfp-64) i/o description pdi pb2 pe0 i serial data in pdo pb3 pe1 o serial data out sck pb1 pb1 i serial clock vcc gnd xtal1 sck pdo pdi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 384 7593a?avr?02/06 at90usb64/128 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial inst ruction to pin pdi. 3. the serial programming instructions will not work if the communication is out of syn- chronization. when in sync. the second byte (0x53), will ec ho back when issuing the third byte of the programming enable instructio n. whether the echo is correct or not, all four bytes of the instruction must be tran smitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time . the memory page is loaded one byte at a time by supplying the 7 lsb of the add ress and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is appli ed for a given address. the program memory page is stored by loading the write progra m memory page instruction with the address lines 15..8. before issuing this command, make sure the instruction load extended address byte has been used to define the msb of the address. the extended address byte is stored until the command is re-issue d, i.e., the command needs only be issued for the first page, and when crossi ng the 64kword boundary. if polling ( rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page. (see table 29- 15 .) accessing the serial programming interface before the flash write operation com- pletes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with t he appropriate write in struction. an eeprom memory location is first automatically erased before new data is wr itten. if polling is no t used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 29-15 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by us ing the read instruct ion which returns the content at the selected address at serial output pdo. when reading the flash memory, use the instruction load extended address byte to define the upper address byte, which is not included in the read program memory instruction. the extended address byte is stored until the command is re-issue d, i.e., the command needs only be issued for the first page, and when crossing the 64kword boundary. 7. at the end of the pr ogramming se ssion, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. table 29-15. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 9.0 ms t wd_erase 9.0 ms 385 7593a?avr?02/06 at90usb64/128 figure 29-11. serial programming waveforms msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample s erial data output 386 7593a?avr?02/06 at90usb64/128 table 29-16. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. load extended address byte 0100 1101 0000 0000 cccc cccc xxxx xxxx defines extended address byte for read program memory and write program memory page. read program memory 0010 h 000 aaaa aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address c : a : b . load program memory page 0100 h 000 xxxx xxxx xx bb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 aaaa aaaa bb xx xxxx xxxx xxxx write program memory page at address c : a : b . read eeprom memory 1010 0000 0000 aaaa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 0000 aaaa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 0000 aaaa bbbb bb00 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 29-1 on page 368 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 29-1 on page 368 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 29-3 on page 369 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro- grammed, ?1? = unprogrammed. 387 7593a?avr?02/06 at90usb64/128 note: a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care 29.8.2 serial progra mming characteristics for characteristics of the serial programming m odule see ?spi timing characteristics? on page 405. 29.9 programming via the jtag interface programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the re set and clock pins is not required. to be able to use the jtag interface, the jtag en fuse must be programmed. the device is default shipped with the fuse programmed. in addi tion, the jtd bit in mcucsr must be cleared. alternatively, if the jtd bit is set, the external reset can be forc ed low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins are available for programming. this provides a means of using the jtag pins as normal port pi ns in running mode while still allowing in-sys- tem programming via the jtag interface. note th at this technique can not be used when using the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be ded- icated for this purpose. during programming the clock frequency of the tc k input must be less than the maximum fre- quency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficientl y low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. 29.9.1 programming specific jtag instructions the instruction register is 4-bit wide, supporti ng up to 16 instructions. the jtag instructions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state between jtag sequences . the state machine sequence for changing the instruction word is shown in figure 29-12 . read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 29-3 on page 369 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 29-16. serial programming instruction set (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte4 388 7593a?avr?02/06 at90usb64/128 figure 29-12. state machine sequence for changing the instruction word 29.9.2 avr_reset (0xc) the avr specific public jtag inst ruction for setting the avr device in the reset mode or taking the device out from the reset mode. the tap contro ller is not reset by this instruction. the one bit reset register is selected as data register. no te that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 29.9.3 prog_enable (0x4) the avr specific public jtag instruction for enabling programming via the jtag port. the 16- bit programming enable register is selected as data register. the active states are the following: ? shift-dr: the programming enable signatur e is shifted into the data register. ? update-dr: the programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid. test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 389 7593a?avr?02/06 at90usb64/128 29.9.4 prog_commands (0x5) the avr specific public jtag instruction fo r entering programming commands via the jtag port. the 15-bit programming command register is selected as data register. the active states are the following: ? capture-dr: the result of the previous co mmand is loaded into the data register. ? shift-dr: the data register is shifted by the tc k input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to the flash inputs ? run-test/idle: one clock cycle is ge nerated, executing the applied command 29.9.5 prog_pageload (0x6) the avr specific public jtag in struction to directly load the flash data page via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte register is copied into a temporary register. a write sequence is initiated that within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new update-dr stat e, starting with the low byte for the first update-dr encountered after entering th e prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the first written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. 29.9.6 prog_pageread (0x7) the avr specific public jtag instruction to dire ctly capture the flash content via the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the active states are the following: ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, st arting with the low byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. ? shift-dr: the flash data byte register is shifted by the tck input. 29.9.7 data registers the data registers are selected by the jtag instruction registers described in section ?pro- gramming specific jtag instructions? on page 387 . the data registers relevant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 390 7593a?avr?02/06 at90usb64/128 29.9.8 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the external reset low. the part is reset as long as there is a high val ue present in the reset register. depending on the fuse settings for the clock options, the part will remain reset for a re set time-out period (refer to ?clock sources? on page 39 ) after releasing the reset register. the output from this data register is not latched, so the reset will take place immediately, as shown in figure 8-1 on page 59 . 29.9.9 programming enable register the programming enable register is a 16-bit register. the contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. when the con- tents of the register is equal to the programmi ng enable signature, programming via the jtag port is enabled. the register is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 29-13. programming enable register 29.9.10 programming command register the programming command register is a 15-bit regist er. this register is used to serially shift in programming commands, and to serially shift out th e result of the previous command, if any. the jtag programming instruction set is shown in table 29-17 . the state sequence when shifting in the programming commands is illustrated in figure 29-15 . tdi tdo d a t a = dq clockdr & prog_enable programming enable 0xa370 391 7593a?avr?02/06 at90usb64/128 figure 29-14. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits 392 7593a?avr?02/06 at90usb64/128 table 29-17. jtag programming instruction set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (2) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 2c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 2d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2e. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2f. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2g. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. poll for page write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 3c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 3d. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3e. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 393 7593a?avr?02/06 at90usb64/128 4g. poll for page write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (6) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6e. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6h. load data low byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (7) 0111110_0 0000000 0111111_0 0000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo table 29-17. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 394 7593a?avr?02/06 at90usb64/128 notes: 1. this command sequence is not required if the seven msb are correctly set by the previo us command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 29-3 on page 369 7. the bit mapping for fuses high byte is listed in table 29-4 on page 370 8. the bit mapping for fuses low byte is listed in table 29-5 on page 370 9. the bit mapping for lock bits byte is listed in table 29-1 on page 368 10. address bits exceeding pcmsb and eeamsb ( table 29-11 and table 29-12 ) are don?t care 11. all tdi and tdo sequences are repr esented by binary digits (0b...). 8d. read fuse low byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (5) 8f. read fuses and lock bits 0111010_00000000 0111110_0 0000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 29-17. jtag programming instruction (continued) set (continued) a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 395 7593a?avr?02/06 at90usb64/128 figure 29-15. state machine sequence for changing/reading the data word 29.9.11 flash data byte register the flash data byte register provides an ef ficient way to load t he entire flash page buffer before executing page write, or to read out/verif y the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 tck cycles loads the content of the temporary register into the flash page buff er. the avr automatically alternates between writing the low and the high byte for each new up date-dr state, starting with the low byte for the first update-dr encountered after entering t he prog_pageload command. the program counter is pre-incremented before writing the low byte, except fo r the first written byte. this ensures that the first data is written to th e address set up by prog_commands, and loading the last location in the page buffer does not ma ke the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr stat e, starting with the low byte for the first cap- test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 396 7593a?avr?02/06 at90usb64/128 ture-dr encountered after entering the prog _pageread command. the program counter is post-incremented after reading each high byte, includ ing the first read byte. this ensures that the first data is captured from the first ad dress set up by prog_commands, and reading the last location in the page makes the progra m counter increment into the next page. figure 29-16. flash data byte register the state machine controlling the flash data by te register is clocked by tck. during normal operation in which eight bits are shifted for each flash byte, the clock cycles needed to navigate through the tap controller automatically feeds th e state machine for the flash data byte regis- ter with sufficient number of clock pulses to complete its operation transparently for the user. however, if too few bits are shifted between each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to en sure that there are at least 11 tck cycles between each update-dr state. 29.9.12 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 29-17 . 29.9.13 entering programming mode 1. enter jtag instructio n avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the program- ming enable register. 29.9.14 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the program- ming enable register. 4. enter jtag instructio n avr_reset and shift 0 in the reset register. tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine 397 7593a?avr?02/06 at90usb64/128 29.9.15 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase comple te using programming instruction 1b, or wait for t wlrh_ce (refer to table 29-13 on page 382 ). 29.9.16 programming the flash before programming the flash a chip erase must be performed, see ?performing chip erase? on page 397. 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address extended high byte using programming instruction 2b. 4. load address high byte using programming instruction 2c. 5. load address low byte using programming instruction 2d. 6. load data using programming instructions 2e, 2f and 2g. 7. repeat steps 5 and 6 for all instruction words in the page. 8. write the page using programming instruction 2h. 9. poll for flash write complete using prog ramming instruction 2i, or wait for t wlrh (refer to table 29-13 on page 382 ). 10. repeat steps 3 to 9 until all data have been programmed. a more efficient data transfer can be achieved using the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b, 2c and 2d. pcword (refer to table 29-11 on page 373 ) is used to address within on e page and must be written as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, start- ing with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to c opy the contents of the flash data byte register into the flash page location an d to auto-increment the program counter before each new word. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2h. 8. poll for flash write complete using prog ramming instruction 2i, or wait for t wlrh (refer to table 29-13 on page 382 ). 9. repeat steps 3 to 8 until all data have been programmed. 29.9.17 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b, 3c and 3d. 4. read data using programming instruction 3e. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be achieved usi ng the prog_pageread instruction: 398 7593a?avr?02/06 at90usb64/128 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b, 3c and 3d. pcword (refer to table 29-11 on page 373 ) is used to address within on e page and must be written as 0. 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction words in the page (or flash), starting with the lsb of the first inst ruction in the page (flash) and ending with the msb of the last instructio n in the page (flash). the c apture-dr state both captures the data from the flash, and also auto-inc rements the program counter after each word is read. note that capture-dr comes before the shift-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been read. 29.9.18 programming the eeprom before programming the eeprom a chip erase must be perfo rmed, see ?performing chip erase? on page 397. 1. enter jtag instruction prog_commands. 2. enable eeprom write usin g programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. write the data using programming instruction 4f. 8. poll for eeprom write comple te using programming instru ction 4g, or wait for t wlrh (refer to table 29-13 on page 382 ). 9. repeat steps 3 to 8 until all data have been programmed. note that the pr og_pageload instruction can not be used when program ming the eeprom. 29.9.19 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming in struction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. note that the prog_pageread instruction can not be us ed when reading the eeprom. 29.9.20 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6a. 3. load data high byte using programming instruct ions 6b. a bit valu e of ?0? will program the corresponding fuse, a ?1? will unprogram the fuse. 4. write fuse high byte using programming instruction 6c. 5. poll for fuse write complete using programming instruction 6d, or wait for t wlrh (refer to table 29-13 on page 382 ). 399 7593a?avr?02/06 at90usb64/128 6. load data low byte using programming in structions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. write fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming instruction 6g, or wait for t wlrh (refer to table 29-13 on page 382 ). 29.9.21 programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write using programming instruction 7a. 3. load data using pr ogramming instructions 7b. a bit va lue of ?0? will program the corre- sponding lock bit, a ?1? will leave the lock bit unchanged. 4. write lock bits using programming instruction 7c. 5. poll for lock bit write comp lete using programming instruction 7d, or wait for t wlrh (refer to table 29-13 on page 382 ). 29.9.22 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instruction 8b. to only read fuse low byte, use programming instruction 8c. to only read lock bits, use programming instruction 8d. 29.9.23 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 an d address 0x02 to read the second and third signature bytes, respectively. 29.9.24 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 400 7593a?avr?02/06 at90usb64/128 30. electrical characteristics 30.1 absolute maximum ratings* 30.2 dc characteristics operating temperature.................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. (5) typ. max. (5) units v il input low voltage,except xtal1 and reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v il1 input low voltage, xtal1 pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v il2 input low voltage, reset pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v v ih2 input high voltage, reset pin v cc = 1.8v - 5.5v 0.9v cc (2) v cc + 0.5 v v ol output low voltage (3) , i ol = 10ma, v cc = 5v i ol = 5ma, v cc = 3v 0.7 0.5 v v oh output high voltage (4) , i oh = -20ma, v cc = 5v i oh = -10ma, v cc = 3v 4.2 2.3 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 k 401 7593a?avr?02/06 at90usb64/128 note: 1. "max" means the highest value where the pin is guaranteed to be read as low 2. "min" means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditi ons (20ma at vcc = 5v, 10ma at vcc = 3v) under steady state conditions (non-transient), t he following must be observed: at90usb64/128: 1.)the sum of all iol, for ports a0-a7, g2, c4-c7 should not exceed 100 ma. 2.)the sum of all iol, for ports c0-c3, g0-g1, d0-d7 should not exceed 100 ma. 3.)the sum of all iol, for ports g3-g5, b0-b7, e0-e7 should not exceed 100 ma. 4.)the sum of all iol, for ports f0-f7 should not exceed 100 ma. if iol exceeds the test conditio n, vol may exceed the related sp ecification. pins ar e not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test co nditions (20ma at vcc = 5v, 10ma at vcc = 3v) under steady state conditions (non-transient), the following must be observed: at90usb64/128: 1)the sum of all ioh, for ports a0-a7, g2, c4-c7 should not exceed 100 ma. 2)the sum of all ioh, for ports c0-c3, g0-g1, d0-d7 should not exceed 100 ma. 3)the sum of all ioh, for ports g3-g5, b0-b7, e0-e7 should not exceed 100 ma. 4)the sum of all ioh, for ports f0-f7 should not exceed 100 ma. 5. all dc characteristics contained in this datasheet are base d on simulation and characterization of other avr microcontrol- lers manufactured in the same process technology. these valu es are preliminary values r epresenting design targets, and will be updated after characterization of actual silicon 6. values with ?power reduction register 1 - prr1? disabled (0x00). i cc power supply current (6) active 1mhz, v cc = 2v (at90usb64/128) 0.8 ma active 4mhz, v cc = 3v (at90usb64/128) 5ma active 8mhz, v cc = 5v (at90usb64/128) 18 ma idle 1mhz, v cc = 2v (at90usb64/128) 0.4 0.75 ma idle 4mhz, v cc = 3v (at90usb64/128) 2.2 ma idle 8mhz, v cc = 5v (at90usb64/128) 8ma power-down mode wdt enabled, v cc = 3v <10 20 a wdt disabled, v cc = 3v <1 3 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns t a = -40 c to 85 c, v cc = 1.8v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. (5) typ. max. (5) units 402 7593a?avr?02/06 at90usb64/128 30.3 external clock drive waveforms figure 30-1. external clock drive waveforms 30.4 external clock drive note: all dc characteristics contained in this datasheet are based on simulation and characterization of other avr microcontrollers manufactured in the same process technology. these values are pre- liminary values representing design targets, and will be updated after characterization of actual silicon. 30.5 maximum speed vs. v cc maximum frequency is depending on v cc. as shown in figure 30-2 , the maximum frequency vs. v cc curve is linear between 2.7v < v cc < 4.5v. v il1 v ih1 table 30-1. external clock drive symbol parameter v cc =1.8-5.5v v cc =2.7-5.5v v cc =4.5-5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 0208016mhz t clcl clock period 500 125 62.5 ns t chcx high time 200 50 25 ns t clcx low time 200 50 25 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 2% 403 7593a?avr?02/06 at90usb64/128 figure 30-2. maximum frequency vs. v cc , at90usb64/128 30.6 2-wire serial inte rface characteristics table 30-2 describes the requirements for devices connected to the 2-wire serial bus. the at90usb64/128 2-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 30-3 . table 30-2. 2-wire serial bus requirements symbol parameter condition min max units vil input low-voltage -0.5 0.3 v cc v vih input high-voltage 0.7 v cc v cc + 0.5 v vhys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ?v vol (1) output low-voltage 3 ma sink current 0 0.4 v tr (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns tof (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns tsp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t low low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - 404 7593a?avr?02/06 at90usb64/128 notes: 1. in at90usb64/128, this parameter is characterized and not 100% tested. 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all at90usb64/128 2-wire serial interface operation. other de vices connected to the 2-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the at90u sb64/128 2-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the at90u sb64/128 2-wire serial interface is (1/f scl - 2/f ck ), thus the low time require- ment will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, at90usb64/128 devices connected to the bus may communicate at full speed (400 khz) with other at90usb64/1 28 devices, as well as any other device with a proper t low acceptance margin. figure 30-3. 2-wire serial bus timing t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s f scl > 100 khz 1.3 ? s table 30-2. 2-wire serial bus requirements (continued) symbol parameter condition min max units t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r 405 7593a?avr?02/06 at90usb64/128 30.7 spi timing characteristics see figure 30-4 and figure 30-5 for details. note: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck > 12 mhz figure 30-4. spi interface timing requirements (master mode) table 30-3. spi timing parameters description mode min typ max 1 sck period master see table 17-4 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master tbd 4 setup master 10 5holdmaster 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave tbd 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 mo si ( data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 406 7593a?avr?02/06 at90usb64/128 figure 30-5. spi interface timing requirements (slave mode) 30.8 hardware boot entran cetiming characteristics figure 30-6. hardware boot timing requirements mi so ( data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 table 30-4. hardware boot timings symbol parameter min max tshrh hwb low setup before reset high 0 thhrh hwb low hold after reset high startuptime(s ut) + time out delay(tout) reset ale/hwb t shrh t hhrh 407 7593a?avr?02/06 at90usb64/128 30.9 adc characteristics ? preliminary data table 30-5. adc characteristics symbol parameter condition min (1) typ (1) max (1) units resolution single ended conversion 10 bits differential conversion gain = 1x or 20x 8bits differential conversion gain = 200x 7bits absolute accuracy (including inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz 22.5lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 1 mhz 4.5 lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz noise reduction mode 2lsb single ended conversion v ref = 4v, v cc = 4v, adc clock = 1 mhz noise reduction mode 4.5 lsb integral non-linearity (inl) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz 0.5 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz 0.25 lsb gain error single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz 2lsb offset error single ended conversion v ref = 4v, v cc = 4v, adc clock = 200 khz 2lsb conversion time free running conversion 13 260 s clock frequency single ended conversion 50 1000 khz avcc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage single ended conversion 1.0 avcc v differential conversion 1.0 avcc - 0.5 v v in input voltage single ended channels gnd v ref v differential conversion 0 avcc v input bandwidth single ended channels 38,5 khz differential channels 4 khz v int1 internal voltage reference 1.1v 1.0 1.1 1.2 v 408 7593a?avr?02/06 at90usb64/128 notes: 1. values are guidelines only. actual values are tbd 30.10 external data memory timing notes: 1. this assumes 50% clock duty cycle. the half period is actually the hi gh time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. th e half period is actually the low time of the external clock, xtal1. v int2 internal voltage reference 2.56v 2.4 2.56 2.8 v r ref reference input resistance 32 k r ain analog input resistance 100 m table 30-6. external data memory characteristics, 4.5 - 5.5 volts, no wait-state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 115 1.0t clcl -10 ns 2t avll address valid a to ale low 57.5 0.5t clcl -5 (1) ns 3a t llax_st address hold after ale low, write access 55 ns 3b t llax_ld address hold after ale low, read access 55 ns 4t avllc address valid c to ale low 57.5 0.5t clcl -5 (1) ns 5t avrl address valid to rd low 115 1.0t clcl -10 ns 6t avwl address valid to wr low 115 1.0t clcl -10 ns 7t llwl ale low to wr low 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) ns 8t llrl ale low to rd low 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) ns 9t dvrh data setup to rd high 40 40 ns 10 t rldv read low to data valid 75 1.0t clcl -50 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 115 1.0t clcl -10 ns 13 t dvwl data setup to wr low 42.5 0.5t clcl -20 (1) ns 14 t whdx data hold after wr high 115 1.0t clcl -10 ns 15 t dvwh data valid to wr high 125 1.0t clcl ns 16 t wlwh wr pulse width 115 1.0t clcl -10 ns table 30-5. adc characteristics (continued) symbol parameter condition min (1) typ (1) max (1) units 409 7593a?avr?02/06 at90usb64/128 table 30-7. external data memory characteristics, 4.5 - 5.5 volts, 1 cycle wait-state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 2.0t clcl -50 ns 12 t rlrh rd pulse width 240 2.0t clcl -10 ns 15 t dvwh data valid to wr high 240 2.0t clcl ns 16 t wlwh wr pulse width 240 2.0t clcl -10 ns table 30-8. external data memory char acteristics, 4.5 - 5.5 volt s, srwn1 = 1, srwn0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse width 365 3.0t clcl -10 ns 15 t dvwh data valid to wr high 375 3.0t clcl ns 16 t wlwh wr pulse width 365 3.0t clcl -10 ns table 30-9. external data memory char acteristics, 4.5 - 5.5 volt s, srwn1 = 1, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse width 365 3.0t clcl -10 ns 14 t whdx data hold after wr high 240 2.0t clcl -10 ns 15 t dvwh data valid to wr high 375 3.0t clcl ns 16 t wlwh wr pulse width 365 3.0t clcl -10 ns table 30-10. external data memory characteristics, 2.7 - 5.5 volts, no wait-state symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 1t lhll ale pulse width 235 t clcl -15 ns 2t avll address valid a to ale low 115 0.5t clcl -10 (1) ns 3a t llax_st address hold after ale low, write access 55ns 410 7593a?avr?02/06 at90usb64/128 notes: 1. this assumes 50% clock duty cycle. the half period is actually the hi gh time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. th e half period is actually the low time of the external clock, xtal1. 3b t llax_ld address hold after ale low, read access 55ns 4t avllc address valid c to ale low 115 0.5t clcl -10 (1) ns 5t avrl address valid to rd low 235 1.0t clcl -15 ns 6t avwl address valid to wr low 235 1.0t clcl -15 ns 7t llwl ale low to wr low 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) ns 8t llrl ale low to rd low 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) ns 9t dvrh data setup to rd high 45 45 ns 10 t rldv read low to data valid 190 1.0t clcl -60 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 235 1.0t clcl -15 ns 13 t dvwl data setup to wr low 105 0.5t clcl -20 (1) ns 14 t whdx data hold after wr high 235 1.0t clcl -15 ns 15 t dvwh data valid to wr high 250 1.0t clcl ns 16 t wlwh wr pulse width 235 1.0t clcl -15 ns table 30-10. external data memory charac teristics, 2.7 - 5.5 volts, no wait-state (continued) symbol parameter 4 mhz oscillator variable oscillator unit min max min max table 30-11. external data memory char acteristics, 2.7 - 5.5 volt s, srwn1 = 0, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 440 2.0t clcl -60 ns 12 t rlrh rd pulse width 485 2.0t clcl -15 ns 15 t dvwh data valid to wr high 500 2.0t clcl ns 16 t wlwh wr pulse width 485 2.0t clcl -15 ns table 30-12. external data memory char acteristics, 2.7 - 5.5 volt s, srwn1 = 1, srwn0 = 0 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse width 735 3.0t clcl -15 ns 15 t dvwh data valid to wr high 750 3.0t clcl ns 16 t wlwh wr pulse width 735 3.0t clcl -15 ns 411 7593a?avr?02/06 at90usb64/128 figure 30-7. external memory timing (srwn1 = 0, srwn0 = 0 table 30-13. external data memory char acteristics, 2.7 - 5.5 volt s, srwn1 = 1, srwn0 = 1 symbol parameter 4 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse width 735 3.0t clcl -15 ns 14 t whdx data hold after wr high 485 2.0t clcl -15 ns 15 t dvwh data valid to wr high 750 3.0t clcl ns 16 t wlwh wr pulse width 735 3.0t clcl -15 ns ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 412 7593a?avr?02/06 at90usb64/128 figure 30-8. external memory timing (srwn1 = 0, srwn0 = 1) figure 30-9. external memory timing (srwn1 = 1, srwn0 = 0) ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 413 7593a?avr?02/06 at90usb64/128 figure 30-10. external memory timing (srwn1 = 1, srwn0 = 1) () the ale pulse in the last period (t4-t7) is only pres ent if the next instruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 t6 414 7593a?avr?02/06 at90usb64/128 31. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) otgtcon 1 page value (0xf8) upint pint7:0 (0xf7) upbchx - - - - - pbyct10:8 (0xf6) upbclx pbyct7:0 (0xf5) uperrx - counter1:0 crc16 timeout pid datapid datatgl (0xf4) ueint epint6:0 (0xf3) uebchx - - - - -byct10:8 (0xf2) uebclx byct7:0 (0xf1) uedatx dat7:0 (0xf0) ueienx flerre nakine - nakoute rxstpe rxoute stallede txine (0xef) uesta1x - - - - - ctrldir currbk1:0 (0xee) uesta0x cfgok overfi underfi zlpseen dtseq1:0 nbusybk1:0 (0xed) uecfg1x epsize2:0 epbk1:0 alloc (0xec) uecfg0x eptype1:0 isosw autosw nyetsdis epdir (0xeb) ueconx stallrq stallrqc rstdt epen (0xea) uerst eprst6:0 (0xe9) uenum epnum2:0 (0xe8) ueintx fifocon nakini rwal nakouti rxstpi rxouti stalledi txini (0xe7) udtst opmode2 tstpckt tstk tstj (0xe6) udmfn fncerr (0xe5) udfnumh fnum10:8 (0xe4) udfnuml fnum7:0 (0xe3) udaddr adden uadd6:0 (0xe2) udien uprsme eorsme wakeupe eorste sofe msofe suspe (0xe1) udint uprsmi eorsmi wakeupi eorsti sofi msofi suspi (0xe0) udcon lsm rmwkup detach (0xdf) otgint stoi hnperri roleexi bcerri vberri srpi (0xde) otgien stoe hnperre roleexe bcerre vberre srpe (0xdd) otgcon 0 hnpreq srpreq srpsel vbushwc vbusreq vbusrqc (0xdc) udpaddh dpacc dpadd10:8 (0xdb) udpaddl dpadd7:0 (0xda) usbint idti bbusti (0xd9) usbsta speed id vbus (0xd8) usbcon usbe host frzclk otgpade idte vbuste (0xd7) uhwcon uimod uide uvcone uvrege (0xd6) reserved (0xd5) reserved (0xd4) reserved (0xd3) reserved (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) udr1 usart1 i/o data register (0xcd) ubrr1h - - - - usart1 baud rate register high byte (0xcc) ubrr1l usart1 baud rate register low byte (0xcb) reserved - - - - - - - - (0xca) ucsr1c umsel11 umsel10 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 pe1 u2x1 mpcm1 (0xc7) reserved - - - - - - - - (0xc6) reserved - - - - - - - - (0xc5) reserved - - - - - - - - (0xc4) reserved - - - - - - - - (0xc3) reserved - - - - - - - - (0xc2) reserved - - - - - - - - (0xc1) reserved - - - - - - - - (0xc0) reserved - - - - - - - - (0xbf) reserved - - - - - - - - 415 7593a?avr?02/06 at90usb64/128 (0xbe) reserved - - - - - - - - (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 - (0xbc) twcr twint twea twsta twsto twwc twen -twie (0xbb) twdr 2-wire serial interface data register (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce (0xb9) twsr tws7 tw s6 tws5 tws4 tws3 - twps1 twps0 (0xb8) twbr 2-wire serial interface bit rate register (0xb7) reserved - - - - - - - - (0xb6) assr - exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b (0xb3) ocr2a timer/counter2 output compare register a (0xb2) tcnt2 timer/counter2 (8 bit) (0xb1) tccr2b foc2a foc2b - - wgm22 cs22 cs21 cs20 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - -wgm21wgm20 (0xaf) updatx pdat7:0 (0xae) upienx flerre nakede - perre txstpe txoute rxstalle rxine (0xad) upcfg2x intfrq7:0 (0xac) upstax cfgok overfi underfi dtseq1:0 nbusybk1:0 (0xab) upcfg1x psize2:0 pbk1:0 alloc (0xaa) upcfg0x ptype1:0 ptoken1:0 pepnum3:0 (0xa9) upconx pfreeze inmode autosw rstdt pen (0xa8) uprst prst6:0 (0xa7) upnum pnum2:0 (0xa6) upintx fifocon nakedi rwal perri txstpi txouti rxstalli rxini (0xa5) upinrqx inrq7:0 (0xa4) uhflen flen7:0 (0xa3) uhfnumh fnum10:8 (0xa2) uhfnuml fnum7:0 (0xa1) uhaddr hadd6:0 (0xa0) uhien uprsme eorsme wakeupe eorste sofe msofe suspe (0x9f) uhint uhupi hsofi rxrsmi rsmedi rsti ddisci dconni (0x9e) uhcon resume reset sofen (0x9d) ocr3ch timer/counter3 - output compare register c high byte (0x9c) ocr3cl timer/counter3 - output compare register c low byte (0x9b) ocr3bh timer/counter3 - output compare register b high byte (0x9a) ocr3bl timer/counter3 - output compare register b low byte (0x99) ocr3ah timer/counter3 - output compare register a high byte (0x98) ocr3al timer/counter3 - output compare register a low byte (0x97) icr3h timer/counter3 - input capture register high byte (0x96) icr3l timer/counter3 - input capture register low byte (0x95) tcnt3h timer/counter3 - counter register high byte (0x94) tcnt3l timer/counter3 - counter register low byte (0x93) reserved - - - - - - - - (0x92) tccr3c foc3a foc3b foc3c - - - - - (0x91) tccr3b icnc3 ices3 - wgm33 wgm32 cs32 cs31 cs30 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) ocr1ch timer/counter1 - output compare register c high byte (0x8c) ocr1cl timer/counter1 - output compare register c low byte (0x8b) ocr1bh timer/counter1 - output compare register b high byte (0x8a) ocr1bl timer/counter1 - output compare register b low byte (0x89) ocr1ah timer/counter1 - output compare register a high byte (0x88) ocr1al timer/counter1 - output compare register a low byte (0x87) icr1h timer/counter1 - input capture register high byte (0x86) icr1l timer/counter1 - input capture register low byte (0x85) tcnt1h timer/counter1 - counter register high byte (0x84) tcnt1l timer/counter1 - counter register low byte (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b foc1c - - - - - (0x81) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 (0x7f) didr1 - - - - - -ain1dain0d (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d (0x7d) - - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 416 7593a?avr?02/06 at90usb64/128 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 (0x7b) adcsrb -acme - - mux5 adts2 adts1 adts0 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 (0x79) adch adc data register high byte (0x78) adcl adc data register low byte (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) xmcrb xmbk - - - - xmm2 xmm1 xmm0 (0x74) xmcra sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 (0x73) timsk5 - -icie5 - ocie5c ocie5b ocie5a toie5 (0x72) timsk4 - -icie4 - ocie4c ocie4b ocie4a toie4 (0x71) timsk3 - -icie3 - ocie3c ocie3b ocie3a toie3 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 (0x6f) timsk1 - -icie1 - ocie1c ocie1b ocie1a toie1 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 (0x6d) reserved - - - - - - - - (0x6c) reserved - - - - - - - - (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 (0x68) pcicr - - - - - - -pcie0 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register (0x65) prr1 prusb - - -prtim3 - - prusart1 (0x64) prr0 prtwi prtim2 prtim0 -prtim1prspi - pradc (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 0x3f (0x5f) sreg i t h s v n z c 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) rampz - - - - - - rampz1 rampz0 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr/ mondr ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 monitor data register 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi data register 0x2d (0x4d) spsr spif wcol - - - - - spi2x 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 0x2b (0x4b) gpior2 general purpose i/o register 2 0x2a (0x4a) gpior1 general purpose i/o register 1 0x29 (0x49) pllcsr - - - pllp2 pllp1 pllp0 plle plock 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 0x25 (0x45) tccr0b foc0a foc0b - - wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - -wgm01wgm00 0x23 (0x43) gtccr tsm - - - - - psrasy psrsync 0x22 (0x42) eearh - - - - eeprom address register high byte 0x21 (0x41) eearl eeprom address register low byte 0x20 (0x40) eedr eeprom data register 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere 0x1e (0x3e) gpior0 general purpose i/o register 0 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 417 7593a?avr?02/06 at90usb64/128 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range $00 - $1f are directly bi t-accessible using the sbi and cbi instructions. in these reg - isters, the value of single bits can be che cked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o reg- isters as data space using ld and st instructions, $20 mu st be added to these addresses. the at90usb64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from $60 - $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr - - - - - - -pcif0 0x1a (0x3a) tifr5 - -icf5 - ocf5c ocf5b ocf5a tov5 0x19 (0x39) tifr4 - -icf4 - ocf4c ocf4b ocf4a tov4 0x18 (0x38) tifr3 - -icf3 - ocf3c ocf3b ocf3a tov3 0x17 (0x37) tifr2 - - - - - ocf2b ocf2a tov2 0x16 (0x36) tifr1 - -icf1 - ocf1c ocf1b ocf1a tov1 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 0x14 (0x34) reserved - - - - - - - - 0x13 (0x33) reserved - - - - - - - - 0x12 (0x32) reserved - - - - - - - - 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 0x0e (0x2e) porte porte7 porte6 porte 5 porte4 porte3 porte2 porte1 porte0 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 0x08 (0x28) portc portc7 portc6 portc 5 portc4 portc3 portc2 portc1 portc0 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 0x02 (0x22) porta porta7 porta6 porta 5 porta4 porta3 porta2 porta1 porta0 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 418 7593a?avr?02/06 at90usb64/128 32. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 eijmp extended indirect jump to (z) pc (eind:z) none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc znone4 eicall extended indirect call to (z) pc (eind:z) none 4 call k direct subroutine call pc knone5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 419 7593a?avr?02/06 at90usb64/128 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (z) none 3 elpm rd, z+ extended load program memory rd (rampz:z), rampz:z rampz:z+1 none 3 mnemonics operands description operation flags #clocks 420 7593a?avr?02/06 at90usb64/128 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 421 7593a?avr?02/06 at90usb64/128 33. ordering information table 33-1. possible order entries ordering code speed (mhz) power supply (v) package operation range product marking at 90usb1287-16au 8-16 2.7 - 5.5 64a industrial (-4 0 to +85c) 90usb1287-16au at90usb1287-16mu 8-16 2.7 - 5.5 64m1 industrial (-40 to +85c) 90usb1287-16mu at 90usb1286-16mu 8-16 2.7 - 5.5 64m1 industrial (-40 to +85c) green 90usb1286-16mu at 90usb647-16au 8-16 2.7 - 5.5 64a industrial (-4 0 to +85c) 90usb1287-16au at90usb647-16mu 8-16 2.7 - 5.5 64m1 industrial (-40 to +85c) 90usb1287-16mu at 90usb646-16mu 8-16 2.7 - 5.5 64m1 industrial (-40 to +85c) green 90usb1286-16mu 422 7593a?avr?02/06 at90usb64/128 34. packaging information package type 64a 64-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 64m1 64-lead, quad flat no lead (qfn) 423 7593a?avr?02/06 at90usb64/128 34.1 tqfp64 index corner 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b 11?~13? pin 64 64 leads thin quad flat package notes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. symbol min nom mm max (2) (2) a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ min nom inch max . 047 . 002 . 006 . 037 . 039 . 041 . 620 . 630 . 640 . 547 . 551 . 555 . 620 . 630 . 640 . 547 . 551 . 555 . 012 . 018 . 004 . 008 . 018 . 030 . 0315 typ 424 7593a?avr?02/06 at90usb64/128 34.2 qfn64 1 index corner 2 3 64 63 62 64x b j k 64x l e exposed die at tac h pa d bottom view top view d e index corner a2 a1 0.08 a c seating plane side view b l e a2 n a1 d / e j / k a 6.47 0.80 min 6.57 nom mm 9.00 bsc 6.67 1.00 0.00 0.05 max . 255 . 031 min . 259 nom inch . 354 bsc 0.50 bsc . 020 bsc 64 . 263 0.40 0.45 0.50 . 016 . 018 . 020 0.17 0.25 0.27 . 007 . 010 . 011 . 039 . 000 . 002 0.75 1.00 . 029 . 039 max note: compliant jedec mo-220 425 7593a?avr?02/06 at90usb64/128 35. errata the revision letter in this section refers to the revision of the at90usb64/128 device. 35.1 rev a ? vbus residual level ? spike on twi pins when twi is enabled ? high current consumption in sleep mode ? async timer interrupt wa ke up from sleep generate multiple interrupts 4. vbus residual level in usb device and host mode, once a 5v level has been detected to the vbus pad, a resid- ual level (about 3v) can be measured on the vbus pin. problem fix/workaround none. 3. spike on twi pins when twi is enabled 100 ns negative spike occurs on sda and scl pins when twi is enabled. problem fix/workaround no known workaround, enable at90usb64/128 twi first versus the others nodes of the twi network. 2. high current consumption in sleep mode if a pending interrupt cannot wake the part up from the selected mode, the current consump- tion will increase during sleep when executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to wake up the part from the sleep mode should be disabled. 1. asynchonous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep and wakeups from an asynchronous timer interrupt and then go back in sleep again it ma y wake up multiple times. problem fix/workaround a software workaround is to wait with performing the sleep instruction until tcnt2>ocr2+1. 1 7593a?avr?02/06 at90usb64/128 table of contents 1 pin configurations ... ................ ................ ................. ................ ............... 3 1.1 disclaimer ............................................................................................................4 2 overview ................ .............. .............. ............... .............. .............. ............ 4 2.1 block diagram ......................................................................................................5 2.2 pin descriptions ...................................................................................................6 3 about code examples ........ .............. ............... .............. .............. ............ 8 4 avr cpu core ................. ................ ................. .............. .............. ............ 9 4.1 introduction ..........................................................................................................9 4.2 architectural overview .........................................................................................9 4.3 alu ? arithmetic logic unit ...............................................................................10 4.4 status register ..................................................................................................11 4.5 general purpose register file ...........................................................................12 4.6 stack pointer ......................................................................................................13 4.7 instruction execution timing ..............................................................................14 4.8 reset and interrupt handling .............................................................................15 5 avr at90usb64/128 memories ................ ................ ................. .......... 18 5.1 in-system reprogrammable flash prog ram memory .......................................18 5.2 sram data memory ..........................................................................................19 5.3 eeprom data memory .... ................. ................ ............. ............ ............. ..........22 5.4 i/o memory ........................................................................................................28 5.5 external memory interface .................................................................................29 6 system clock and clock opti ons ........... ................. ................ ............. 38 6.1 clock systems and their distribution .................................................................38 6.2 clock sources ....................................................................................................39 6.3 low power crystal oscillator .............................................................................40 6.4 low frequency crystal oscillator ......... .............................................................43 6.5 calibrated internal rc oscillator .......................................................................43 6.6 128 khz internal oscillator .................................................................................45 6.7 external clock ....................................................................................................46 6.8 clock output buffer ............................................................................................47 6.9 timer/counter oscillator ....................................................................................47 6.10 system clock prescaler .....................................................................................47 6.11 pll .....................................................................................................................49 2 7593a?avr?02/06 at90usb64/128 7 power management and sleep modes ........... .............. .............. .......... 52 7.1 idle mode ...........................................................................................................53 7.2 adc noise reduction mode ..............................................................................53 7.3 power-down mode .............................................................................................53 7.4 power-save mode ..............................................................................................53 7.5 standby mode ....................................................................................................54 7.6 extended standby mode ....................................................................................54 7.7 power reduction register .................................................................................55 7.8 minimizing power consumption ............ .............................................................56 8 system control and reset .... .............. .............. .............. .............. ........ 58 8.1 internal voltage reference ................................................................................63 8.2 watchdog timer .................................................................................................63 9 interrupts ............... .............. .............. ............... .............. .............. .......... 69 9.1 interrupt vectors in at90usb64/128 . ................................................................69 10 i/o-ports ............... ................ .............. ............... .............. .............. .......... 73 10.1 introduction ........................................................................................................73 10.2 ports as general digital i/o ...............................................................................74 10.3 alternate port functions ....................................................................................78 10.4 register description for i/o-ports ......................................................................91 11 external interrupts .......... ................ ................. .............. .............. .......... 95 12 timer/counter0, timer/counter1, and timer/counter3 prescalers ... 99 12.1 internal clock source ......................... ................................................................99 12.2 prescaler reset .................................................................................................99 12.3 external clock source .......................... .............................................................99 12.4 general timer/counter control register ? gtccr ........................................100 13 8-bit timer/counter0 with pwm ................... .............. .............. ........... 101 13.1 overview ..........................................................................................................101 13.2 timer/counter clock sources ..........................................................................102 13.3 counter unit .....................................................................................................102 13.4 output compare unit .......................................................................................103 13.5 compare match output unit ............................................................................105 13.6 modes of operation .........................................................................................106 13.7 timer/counter timing diagrams ......................................................................110 13.8 8-bit timer/counter register descriptio n .........................................................111 3 7593a?avr?02/06 at90usb64/128 14 16-bit timer/counter (timer/counter1 and timer/counter3) ........... 118 14.1 overview ..........................................................................................................118 14.2 accessing 16-bit registers ..............................................................................120 14.3 timer/counter clock sources ..........................................................................123 14.4 counter unit .....................................................................................................123 14.5 input capture unit ............................................................................................125 14.6 output compare units .....................................................................................127 14.7 compare match output unit ............................................................................128 14.8 modes of operation .........................................................................................130 14.9 timer/counter timing diagrams ......................................................................137 14.10 16-bit timer/counter register descripti on .......................................................139 15 8-bit timer/counter2 with pwm a nd asynchronous operation ...... 150 15.1 overview ..........................................................................................................150 15.2 timer/counter clock sources ..........................................................................151 15.3 counter unit .....................................................................................................151 15.4 output compare unit .......................................................................................152 15.5 compare match output unit ............................................................................154 15.6 modes of operation .........................................................................................155 15.7 timer/counter timing diagrams ......................................................................159 15.8 8-bit timer/counter register descriptio n .........................................................161 15.9 asynchronous operation of the timer/counter ................................................166 15.10 timer/counter prescaler ..................................................................................170 16 output compare modulator (ocm1c0a) .. ................ .............. ........... 171 16.1 overview ..........................................................................................................171 16.2 description .......................................................................................................171 17 serial peripheral interface ? spi ......... .............. .............. ............ ........ 173 17.1 ss pin functionality .........................................................................................177 17.2 data modes ......................................................................................................180 18 usart .................. .............. .............. .............. .............. .............. ........... 182 18.1 overview ..........................................................................................................182 18.2 clock generation .............................................................................................183 18.3 frame formats ................................................................................................186 18.4 usart initialization .........................................................................................188 18.5 data transmission ? the usart transmitter ................................................189 18.6 data reception ? the usart receiver ..........................................................191 4 7593a?avr?02/06 at90usb64/128 18.7 asynchronous data reception ........................................................................195 18.8 multi-processor communication mode . ...........................................................198 18.9 usart register description ...........................................................................199 18.10 examples of baud rate setting .......................................................................204 19 usart in spi mode .......... .............. .............. .............. .............. ........... 207 19.1 overview ..........................................................................................................207 19.2 clock generation .............................................................................................208 19.3 spi data modes and timing ............................................................................208 19.4 frame formats ................................................................................................209 19.5 data transfer ...................................................................................................211 19.6 usart mspim register description ...............................................................213 19.7 avr usart mspim vs. avr spi ...................................................................215 20 2-wire serial interface ..... ................ .............. .............. .............. ........... 217 20.1 features ...........................................................................................................217 20.2 2-wire serial interface bus definition ...............................................................217 20.3 data transfer and frame format ....................................................................218 20.4 multi-master bus systems, arbitratio n and synchronization ...........................221 20.5 overview of the twi module ............................................................................222 20.6 twi register description .................................................................................225 20.7 using the twi ..................................................................................................228 20.8 transmission modes ...... ..................................................................................232 20.9 multi-master systems and arbitration ..............................................................245 21 usb controller .......... ................ ................ ................. ................ ........... 247 21.1 features ...........................................................................................................247 21.2 block diagram ..................................................................................................247 21.3 typical application impl ementation .................................................................248 21.4 general operating modes ................................................................................251 21.5 power modes ...................................................................................................256 21.6 speed control ..................................................................................................257 21.7 memory access capability ................................................................................258 21.8 memory management ......................................................................................258 21.9 pad suspend ...................................................................................................259 21.10 otg timers customizing ..................................................................................260 21.11 plug-in detection ..............................................................................................261 21.12 id detection ......................................................................................................262 5 7593a?avr?02/06 at90usb64/128 21.13 registers description .......................................................................................262 21.14 usb software operating modes ......................................................................267 22 usb device operating modes ................ ................. ................ ........... 269 22.1 introduction ......................................................................................................269 22.2 power-on and reset ..........................................................................................269 22.3 speed identification on startup .........................................................................269 22.4 endpoint reset ..................................................................................................270 22.5 usb reset .........................................................................................................270 22.6 endpoint selection ............................................................................................270 22.7 endpoint activation ...........................................................................................270 22.8 address setup .................................................................................................271 22.9 suspend, wake-up and re sume .....................................................................272 22.10 detach ..............................................................................................................272 22.11 remote wake-up .............................................................................................273 22.12 stall request .................................................................................................273 22.13 control endpoint management ...................................................................274 22.14 out endpoint management .............................................................................275 22.15 in endpoint management .................................................................................277 22.16 isochronous mode ...........................................................................................278 22.17 overflow ...........................................................................................................279 22.18 interrupts ..........................................................................................................279 22.19 registers ..........................................................................................................281 23 usb host operating modes .. ................ ................. ................ ............. 293 23.1 pipe description ...............................................................................................293 23.2 detach ..............................................................................................................293 23.3 power-on and reset ........................................................................................293 23.4 device detection ..............................................................................................294 23.5 pipe selection ..................................................................................................294 23.6 pipe configuration ...........................................................................................294 23.7 usb reset .......................................................................................................296 23.8 address setup .................................................................................................296 23.9 remote wake-up de tection .............................................................................296 23.10 usb pipe reset ...............................................................................................296 23.11 pipe data access .............................................................................................296 23.12 control pipe management ...............................................................................297 6 7593a?avr?02/06 at90usb64/128 23.13 out pipe management ...................................................................................297 23.14 in pipe management .......................................................................................298 23.15 interrupt system ...............................................................................................299 23.16 registers ..........................................................................................................300 24 analog comparator .......... .............. .............. .............. .............. ........... 313 24.1 analog comparator mult iplexed input ..............................................................315 25 analog to digital converte r - adc .............. .............. .............. ........... 316 25.1 features ...........................................................................................................316 25.2 operation .........................................................................................................317 25.3 starting a conversion ......................................................................................318 25.4 prescaling and conversion timing ..................................................................319 25.5 changing channel or refe rence selection ......................................................322 25.6 adc noise canceler ........................................................................................323 25.7 adc conversion result ...................................................................................327 25.8 adc register description .................. ..............................................................329 26 jtag interface and on-chip debug system ................... .................. 335 26.1 overview ..........................................................................................................335 26.2 test access port ? tap ...................................................................................335 26.3 tap controller .................................................................................................337 26.4 using the boundary-scan chain ......................................................................338 26.5 using the on-chip debug system ....................................................................338 26.6 on-chip debug specific jtag instructions ......................................................339 26.7 on-chip debug related register in i/ o memory .............................................340 26.8 using the jtag programming capabilit ies .....................................................340 26.9 bibliography .....................................................................................................340 27 ieee 1149.1 (jtag) bounda ry-scan ............ .............. .............. ........... 341 27.1 features ...........................................................................................................341 27.2 system overview .............................................................................................341 27.3 data registers .................................................................................................341 27.4 boundary-scan specific jtag instructions ......................................................343 27.5 boundary-scan related register in i/ o memory .............................................344 27.6 boundary-scan chain ......................................................................................345 27.7 at90usb64/128 boundary-scan order ... ........................................................348 27.8 boundary-scan description language files ....................................................351 7 7593a?avr?02/06 at90usb64/128 28 boot loader support ? read-while-w rite self-programming ......... 352 28.1 boot loader features ......................................................................................352 28.2 application and boot loader flash sections ...................................................352 28.3 read-while-write and no read-while-wri te flash sections ..........................352 28.4 boot loader lock bits ......................................................................................355 28.5 entering the boot loader program ..................................................................356 28.6 addressing the flash during self-pro gramming ..............................................360 28.7 self-programming the flash ............................................................................361 29 memory programming ........ .............. ............... .............. .............. ........ 368 29.1 program and data memory lock bits ..............................................................368 29.2 fuse bits ..........................................................................................................369 29.3 signature bytes ................................................................................................371 29.4 calibration byte ................................................................................................371 29.5 parallel programming pa rameters, pin mapp ing, and commands .................371 29.6 parallel programming ......................................................................................374 29.7 serial downloading ..........................................................................................382 29.8 serial programming pin mapping ....................................................................383 29.9 programming via the jtag interface . ..............................................................387 30 electrical characteristics ... .............. ............... .............. .............. ........ 400 30.1 absolute maximum ratings* ............................................................................400 30.2 dc characteristics ...........................................................................................400 30.3 external clock drive waveforms .......... ...........................................................402 30.4 external clock drive ........................................................................................402 30.5 maximum speed vs. v cc ........................................................................................................................ 402 30.6 2-wire serial interface characteristics .............................................................403 30.7 spi timing characteristics ...............................................................................405 30.8 hardware boot entrancet iming characteristics ..............................................406 30.9 adc characteristics ? pr eliminary data ..........................................................407 30.10 external data memory timing .........................................................................408 31 register summary ............ .............. .............. .............. .............. ........... 414 32 instruction set summary ... .............. ............... .............. .............. ........ 418 33 ordering information .......... .............. ............... .............. .............. ........ 421 34 packaging information ....... .............. ............... .............. .............. ........ 422 34.1 tqfp64 ...........................................................................................................423 8 7593a?avr?02/06 at90usb64/128 34.2 qfn64 .............................................................................................................424 35 errata ........... ................ ................ ................. ................ .............. ........... 425 35.1 rev a ...............................................................................................................425 printed on recycled paper. 7593a?avr?02/06 ? atmel corporation 2006 . all rights reserved. atmel ? , logo and combinations thereof, are regist ered trademarks, and everywhere you are ? are the trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseq uential, punitive, special or i nciden- tal damages (including, without limitation, dam ages for loss of profits, business inte rruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically providedot- herwise, atmel products are not suitable for, and shall not be us ed in, automotive applications. atmel?satmel?s products are no t intended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature |
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